KS8995MAL Micrel Inc, KS8995MAL Datasheet - Page 11

• Manufacturer Part Number: KS8995MAL
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KS8995MAL

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• For Use With: 576-1017 - BOARD EVAL EXPERIMENT KS8995M
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note:
1. P = Power supply.
2. PU = Strap pin pull-up.
May 2005
KS8995MA
Pin Number
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/ internal pull-up.
Ipd = Input w/ internal pull-down.
Ipd/O = Input w/ internal pull-down during reset, output pin otherwise.
Ipu/O = Input w/ internal pull-up during reset, output pin otherwise.
NC = No connect.
PD = Strap pin pull-down.
67
68
69
70
71
72
73
74
75
76
81
61
62
63
64
65
66
77
78
79
80
Pin Name
PMRXDV
PMRXER
SMRXDV
PMRXD3
PMRXD2
PMRXD1
PMRXD0
SMTXEN
SMTXER
SMRXD3
SMRXD2
SMTXD3
SMTXD2
SMTXD1
SMTXD0
SMRXC
SMTXC
VDDIO
GNDD
PCRS
PCOL
Type
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Gnd
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
I/O
P
(1)
Port
5
5
5
5
5
5
5
5
Pin Function
PHY[5] MII receive data valid.
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
PHY[5] MII receive error. Strap option: PD (default) = 1522/1518 bytes;
PU = packet size up to 1536 bytes.
PHY[5] MII carrier sense/force duplex mode. See “Register 76” for
port 4 only. PD (default) = force half-duplex if auto-negotiation is
disabled or fails. PU = force full-duplex if auto-negotiation is disabled
or fails.
PHY[5] MII collision detect/force flow control. See “Register 66” for
port 4 only. PD (default) = no force flow control. normal operation. PU =
force flow control.
Switch MII transmit enable.
Switch MII transmit bit 3.
Switch MII transmit bit 2.
Switch MII transmit bit 1.
Switch MII transmit bit 0.
Switch MII transmit error.
Switch MII transmit clock. Input in MAC mode, output in PHY mode MII.
Digital ground.
3.3V digital V
Switch MII receive clock. Input in MAC mode, output in PHY mode MII.
Switch MII receive data valid
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = enable switch MII full-duplex flow control.
Switch MII receive bit 2. Strap option: PD (default) = switch MII in full
duplex mode; PU = switch MII in half-duplex mode.
11
DD
(2)
for digital I/O circuitry
M9999-051305
Micrel, Inc.