AT88SA10HS-TSU-T Atmel, AT88SA10HS-TSU-T Datasheet - Page 11

• Manufacturer Part Number: AT88SA10HS-TSU-T
• Description: IC HOST AUTHENTICATION SOT23-3
• Manufacturer: Atmel
• Series: CryptoAuthentication™r
• Type: Authentication Chipr

Specifications of AT88SA10HS-TSU-T

• Applications: Networking & Communications
• Mounting Type: Surface Mount
• Package / Case: SOT-23-3
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: 1 Wire
• Minimum Operating Temperature: - 40 C
• Number Of Timers: 1
• Program Memory Size: 72 bit
• Program Memory Type: ROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.4.1. IO Timeout
3.4.2. Synchronization Procedures
3.5.
3.6.
8595B–SMEM–09/09
After a leading transition for any data token has been received, the AT88SA10HS will expect another token to be
transmitted within a t
AT88SA10HS assumes that the synchronization with the host is lost and transitions to a sleep state.
After the AT88SA10HS receives the last bit of a command block, this timeout circuitry is disabled. If the command is
properly formatted, then it is re-enabled with the first transmit token that occurs after t
in the command, then it is re-enabled with the first transmit token that occurs after t
In order to limit the active current if the AT88SA10HS is inadvertently awakened, the IO timeout is also enabled when
the AT88SA10HS wakes up. If the first token does not come within the t
back to sleep without performing any operations.
When the system and the AT88SA10HS fall out of synchronization, the system will ultimately end up sending a transmit
flag which will not generate a response from the AT88SA10HS. The system should implement its own timeout which
waits for t
send a Wake token and after t
successful.
It may be possible that the system does not get the 0x11 code from the AT88SA10HS for one of the following reasons:
1.
2.
3.
Watchdog Failsafe
After the Wake token has been received by the AT88SA10HS, a watchdog counter is started within the chip. After
t
whether some IO transmission is in progress. There is no way to reset the counter other than to put the chip to sleep
and wake it up again.
This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state
machines of the AT88SA10HS including any IO synchronization issue, power consumption will fall to the low sleep
level automatically.
Byte & Bit Ordering
The AT88SA10HS is a little-endian chip:
• All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order
• Data is transferred to/from the AT88SA10HS least significant bit first on the bus.
• In this document, the most significant bit and/or byte appears towards the left hand side of the page.
WATCHDOG
received.
The system did not wait a full t
interpreted the Wake token and Transmit flag as data bits. Recommended resolution is to wait twice the t
delay and re-issue the Wake token.
The AT88SA10HS went into the sleep mode for some reason while the system was transmitting data. In this case,
the AT88SA10HS will interpret the next data bit as a wake token, but ignore some of the subsequently transmitted
bits during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a
legal flag, though the following bytes would not be interpreted as a legal command due to an incorrect count or the
lack of a correct CRC. Recommended resolution is to wait the t
There are some internal error conditions within the AT88SA10HS which will be automatically reset after a t
WATCHDOG
IO pin idle for this interval and issue the Wake token.
TIMEOUT
, the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or
interval, see below. There is no way to externally reset the AT88SA10HS – the system should leave the
during which time the AT88SA10HS should go to sleep automatically. At this point, the system should
AT88SA10HS Host Authentication Chip [Preliminary]
TIMEOUT
interval. If the leading edge of the next token is not received within this period of time, the
WLO
+ t
TIMEOUT
WHI
, a Transmit token. The 0x11 status indicates that the resynchronization was
delay with the IO signal idle in which case the AT88SA10HS may have
TIMEOUT
TIMEOUT
delay and re-issue the Wake token.
interval, then the AT88SA10HS will go
PARSE
PARSE
.
+ t
EXEC
. If there is an error
TIMEOUT
11