KSZ8995XA Micrel Inc, KSZ8995XA Datasheet - Page 31

• Manufacturer Part Number: KSZ8995XA
• Description: IC SWITCH 10/100 5PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8995XA

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 5
• Internal Memory Buffer Size: 64
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1642 - BOARD EVALUATION FOR KSZ8995XA
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1042

September 2008
Address
3
2
1
0
Register 3 (0x03): Global Control 1
7
6
5
4
3
2
1
Name
Enable PHY MII
Buffer share mode
UNH mode
Link change age
Pass all frames
Reserved
IEEE 802.3x transmit
flow control disable
IEEE 802.3x receive
flow control disable
Frame length field
check
Aging enable
Fast age enable
1, link change from “link” to “no link” will cause fast
1, turn on fast age (800µs)
Description
1, enable PHY MII interface (note: if not enabled, the
switch will tri-state all outputs.)
1, buffer pool is shared by all ports. A port can use
more buffer when other ports are not busy.
0, a port is only allowed to use 1/5 of the buffer pool.
1, the switch will drop packets with 0x8808 in T/L
filed, or DA=01-80-C2-00-00-01.
0, the switch will drop packets qualified as “flow
control” packets.
aging (<800µs) to age address table faster. After an
age cycle is complete, the age logic will return to
normal (300 ±75 seconds). Note: If any port is
unplugged, all addresses will be automatically aged
out.
1, switch all packets including bad ones. Used solely
for debugging purpose. Works in conjunction with
sniffer mode.
Reserved
0, will enable transmit flow control based on AN
result
1, will not enable transmit flow control regardless of
AN result.
0, will enable receive flow control based on AN result
1, will not enable receive flow control regardless of
AN result.
Note: Bit 5 and bit 4 default values are controlled by
the same pin, but they can be programmed
independently.
1, will check frame length field in the IEEE packets.
If the actual length does not match, the packet will
be dropped. (for L/T < 1500)
1, Enable age function in the chip
0, Disable aging function
31
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Pin LED[5][1] strap
option. Pull-down
(0): isolate. Pull-up
(1): Enable. Note:
LED[5][1] has
internal pull-up.
Pin PMRXD3 strap
option. Pull-down
(0):
Enable TX flow
control. Pull-up (1):
Disable TX/RX flow
control.
Note: PMRXD3 has
internal pull-down.
Pin PMRXD3 strap
option. Pull-down
(0):
Enable RX flow
control. Pull-up (1):
Disable TX/RX flow
control.
Note: PMRXD3 has
internal pull-down.
Pin LED[5][2] strap
option. Pull-down
(0): Aging disable.
Pull-up (1): Aging
Enable.
Note: LED[5][2] has
internal pull-up.
M9999-091508
Default
0x1
0
0
0
0
0
0