KSZ8993M Micrel Inc, KSZ8993M Datasheet - Page 20

• Manufacturer Part Number: KSZ8993M
• Description: IC SWITCH 10/100 3PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8993M

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Supply Voltage (min): 1.71/3.135V
• Power Dissipation: 800mW
• Supply Current: 0.1/0.19A
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1037

Functional Description
The KS8993M contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2
managed switch.
The KS8993M has the flexibility to reside in either a managed or unmanaged design. In a managed design, the
host processor has complete control of the KS8993M via the SMI interface, MIIM interface, SPI bus, or I
An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
On the media side, the KS8993M supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports, and
100BASE-FX on PHY port 1. The KS8993M can be used as a media converter.
The KS8993ML is the single supply version with all the identical rich features of the KS8993M. In the KS8993ML
version, pin number 22 provides 1.8V output power to the KS8993ML’s V
to the Pin Description table for information about pin 22 (Pin Description and I/0 Assignment).
Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make
the design more efficient and allow for lower power consumption and smaller chip die size.
Functional Overview: Physical Layer Transceiver
100BASE-TX Transmit
The 100BASE-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ to
NRZI conversion, MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which
converts the MII data from the MAC into a 125MHz serial bit stream. The data and control stream is then
converted into 4B/5B coding and followed by a scrambler. The serialized data is further converted from NRZ to
NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 3.01 KΩ
resistor for the 1:1 transformer ratio. It has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD
standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also
incorporated into the 100BASE-TX transmitter.
100BASE-TX Receive
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3 to NRZI conversion,
data and clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding and serial-to-parallel
conversion. The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI)
over the twisted pair cable. Since the amplitude loss and phase distortion is a function of the length of the cable,
the equalizer has to adjust its characteristics to optimize the performance. In this design, the variable equalizer
will make an initial estimation based on comparisons of incoming signal strength against some known cable
characteristics, then it tunes itself for optimization. This is an ongoing process and can self adjust against
environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is
used to compensate for the effect of base line wander and improve the dynamic range. The differential data
conversion circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is
then used to convert the NRZI signal into the NRZ format. The signal is then sent through the de-scrambler
followed by the 4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the
input data to the MAC.
Micrel, Inc.
April 2005
20
DDC
, V
DDA
, and V
DDAP
KS8993M/ML/MI
power pins. Refer
M9999-041205
2
C bus.