CS5307GDWR24 ON Semiconductor, CS5307GDWR24 Datasheet - Page 12

• Manufacturer Part Number: CS5307GDWR24
• Description: IC CTRLR BUCK 4PH VRM 9.0 24SOIC
• Manufacturer: ON Semiconductor
• Type: Step-Down (Buck)r

Specifications of CS5307GDWR24

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Frequency - Switching: 200kHz ~ 800kHz
• Voltage - Input: 4.5 ~ 14 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -
• Other names: CS5307GDWR24OSTR

employing both “slow” and “fast” voltage regulation. The
internal error amplifier performs the slow regulation.
Depending on the gain and frequency compensation set by
the amplifier’s external components, the error amplifier will
typically begin to ramp its output to react to changes in the
output voltage in one or two PWM cycles. Fast voltage
feedback is implemented by a direct connection from Vcore
to the non–inverting pin of the PWM comparator via the
summation with the inductor current, internal ramp and
offset. A rapid increase in output current will produce a
negative offset at Vcore and at the output of the summer.
This will cause the PWM duty cycle to increase almost
instantly. Fast feedback will typically adjust the PWM duty
cycle in one PWM cycle.
at a 50% duty cycle) is added to the inductor current ramp
at the positive terminal of the PWM comparator. This
additional ramp compensates for propagation time delays
from the current sense amplifier (CSA), the PWM
comparator and the MOSFET gate drivers. As a result, the
minimum ON time of the controller is reduced and lower
duty–cycles may be achieved at higher frequencies. Also,
the additional ramp reduces the reliance on the inductor
current ramp and allows greater flexibility when choosing
the output inductor and the R
feedback components from V
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be:
corresponding duty cycle, Ext_Ramp is the peak–to–peak
external steady–state ramp at 0 A, G
amplifier gain (nominally 2.65 V/V) and the channel startup
offset is typically 0.60 V. The magnitude of the Ext_Ramp
can be calculated from:
and the input voltage is 12.0 V, the duty cycle (D) will be
1.700/12.0 or 14.2%. Int_Ramp will be 115 mV/50% 14.2%
= 33 mV. Realistic values for R
0.015 F and 650 kHz. Using these and the previously
mentioned formula, Ext_Ramp will be 15.0 mV.
changes, there must also be a change in the output voltage.
Ext_Ramp + D @ (V IN * V OUT ) (R CSx @ C CSx @ f SW )
Enhanced V
As shown in Figure 14, an internal ramp (nominally 115 mV
Including both current and voltage information in the
Int_Ramp is the “partial” internal ramp value at the
For example, if V
If the COMP pin is held steady and the inductor current
V COMP + V OUT @ 0 A ) Channel_Startup_Offset
V COMP + 1.700 V ) 0.60 V ) 33 mV
) Int_Ramp ) G CSA @ Ext_Ramp 2
2
responds to disturbances in V
+ 2.353 Vdc.
OUT
) 2.65 V V @ 15.0 mV 2
at 0 A is set to 1.700 V with AVP
CSx
CORE
CSx
C
, C
CSx
to the CSx pin.
CSA
CSx
time constant of the
is the current sense
and f
SW
are 10 k ,
CORE
http://onsemi.com
by
CS5307
12
I OUT,PEAK + (V COMP * V OUT * Offset) (R S @ G CSA )
Or, in a closed loop configuration when the output current
changes, the COMP pin must move to keep the same output
voltage. The required change in the output voltage or COMP
pin depends on the scaling of the current feedback signal and
is calculated as:
Single Stage Impedance + DV OUT DI OUT + R S @ G CSA
impedance divided by 4.
the converter will respond during the first few microseconds
of a transient before the feedback loop has repositioned the
COMP pin.
fixed level. Before T1, the converter is in normal
steady–state operation. The inductor current provides a
portion of the PWM ramp through the current sense
amplifier. The PWM cycle ends when the sum of the current
ramp, the “partial” internal ramp voltage signal and offset
exceed the level of the COMP pin. At T1, the output current
increases and the output voltage sags. The next PWM cycle
begins and the cycle continues longer than previously while
the current signal increases enough to make up for the lower
voltage at the V
output voltage remains lower than at light load and the
average current signal level (CSx output) is raised so that the
sum of the current and voltage signal is the same as with the
original load. In a closed loop system, the COMP pin would
move higher to restore the output voltage to the original
level.
SWNODE
V
Internal Ramp
CSA Out w/
Exaggerated
Delays
COMP–Offset
CSA Out + Ramp + CS
The single–phase power stage output impedance is:
The total output impedance will be the single stage
The output impedance of the power stage determines how
The peak output current can be calculated from:
Figure 15 shows the step response of the COMP pin at a
FB
(V
OUT
)
Figure 15. Open Loop Operation
DV + R S @ G CSA @ DI OUT
FB
pin and the cycle ends at T2. After T2, the
REF
T1
T2