CS5307GDWR24 ON Semiconductor, CS5307GDWR24 Datasheet
CS5307GDWR24
Specifications of CS5307GDWR24
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CS5307GDWR24 Summary of contents
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... WW = Work Week PIN CONNECTIONS 1 GND OCSET R OSC CS1 CS2 CS3 CS4 CS REF V DRP V FB COMP SS ORDERING INFORMATION Device Package CS5307GDW24 SO–24L CS5307GDWR24 SO–24L GATE1 GATE2 GATE3 GATE4 V ID0 V ID1 V ID2 V ID3 V ID4 PWRGDS PWRGD Shipping 30 Units/Rail 1000 Tape & Reel Publication Order Number: ...
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V 6.2 V 5.5 V GND GND OCSET R OSC CS1 CS2 CS3 CS4 CS REF V DRP V FB COMP SS PWRGD V ID4 V ID3 V ID2 V ID1 V ID0 Figure 1. Application Diagram ...
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MAXIMUM RATINGS* Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) Package Thermal Resistance Junction–to–Case Junction–to–Ambient Lead Temperature Soldering: Reflow (Note 1.) MSL 1. 60 second maximum above 183 C. *The maximum package power ...
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ELECTRICAL CHARACTERISTICS (0 C & COMP SS VCC Parameter Voltage Identification DAC (0 = Connected to GND Open or Pull–Up to Internal 3.3 V ...
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ELECTRICAL CHARACTERISTICS (continued COMP SS VCC Parameter Voltage Identification DAC (0 = Connected to GND Open or Pull–Up to Internal 3 External Voltage ...
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ELECTRICAL CHARACTERISTICS (continued COMP SS VCC Parameter Gates Rise Time 0.8 V < GATEx < 2 Fall Time 2.0 V > ...
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ELECTRICAL CHARACTERISTICS (continued COMP SS VCC Parameter Current Sense Amplifiers OCSET Input Bias Current OCSET = 0 V Current Sense Input to OCSET OCSET/(CSx–CS Gain OCSET < ...
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Dominant Dominant Reset Reset Dominant Set Figure 2. Block Diagram CS5307 Dominant Dominant Reset Reset Delay http://onsemi.com 8 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 900 800 700 600 500 400 300 200 100 Value (k ) OSC Figure 3. Oscillator Frequency ...
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TYPICAL PERFORMANCE CHARACTERISTICS 2.9 Current Sense Amp 2 Comparator 2.7 Current Sense Amp to V Gain DRP 2.6 2.5 Current Sense Amp to PWM Comparator 2.4 2.3 2 Figure ...
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... Overview The CS5307 DC/DC controller from ON Semiconductor 2 was developed using the Enhanced V topology. Enhanced combines the original V topology with peak current–mode control for fast transient response and current sensing capability. The addition of an internal PWM ramp and implementation of fast–feedback directly from Vcore has improved transient response and simplified design ...
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Enhanced V responds to disturbances in V employing both “slow” and “fast” voltage regulation. The internal error amplifier performs the slow regulation. Depending on the gain and frequency compensation set by the amplifier’s external components, the error amplifier will ...
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R CSx SWNODE Lx C CSx RLx V OUT (V ) CORE + + 2 Figure 16. Enhanced V Control Employing Lossless Inductive Current Sensing and Internal Ramp Inductive Current Sensing For lossless sensing, current can be sensed across the ...
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Due to the faster than ideal RC time constant, there is an overshoot of 50% and the overshoot decays with a 200 s time constant. With this compensation, the OCSET pin threshold must be set more than 50% above the ...
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PWRGD PWRGD PWRGD low high Ç Ç Ç Ç Ç Ç HIGH Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç LOW É É É Ç Ç Ç É É É Ç Ç Ç É É É ...
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Table 1. Fault Protection Logic Fault Modes Undervoltage Lockout VID–11111 Phase Over Current (0.33 V Limit) The latest VRM and processor specifications require a power supply to turn its output off in the event of a 11111 VID code. When ...
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For decreasing current: Dt DEC + OUT ) For typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. Thus, ...
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MAX dI/dt occurs in first few PWM cycles Vi TBD – ESR / Figure 22. Calculating the Input Inductance 4. Input Inductor Selection ...
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As with the output inductor, the input inductor must support the maximum current without saturating the inductor. Also, for an inexpensive iron powder core, such as the –26 or –52 from Micrometals, the inductance “swing” with DC bias must be ...
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Vf is the forward voltage of the MOSFET’s intrinsic diode diode at the converter output current. t_nonoverlap is the non–overlap time between the upper and lower gate drivers to prevent cross conduction. This time is usually specified in the ...
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R CS1 MAX C CS1 R CSx MAX C CSx V = VID – (I CORE = VID – I Figure 26. V Tuning Waveforms. The RC Time DRP Constant of the Current Sense ...
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Figure 28. V Tuning Waveforms. The RC Time DRP Constant of the Current Sense Network Is Optimal: V and V Respond to the Load Current Quickly DRP OUT Without Overshooting. For resistive current sensing, choose the current sense network (R ...
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Figure 31. At Full–Load the Peak–to–Peak Voltage Ripple on the COMP Pin Should Be Less than 20 mV for a Well–Tuned/Stable Controller. Higher COMP Voltage Ripple Will Contribute to Output Voltage Jitter. V OCSET + (I OUT,LIM ) DI Lo ...
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... JAPAN: ON Semiconductor, Japan Customer Focus Center 2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051 Phone: 81–3–5773–3850 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14 ...