LTC1628CG-PG Linear Technology, LTC1628CG-PG Datasheet - Page 24

• Manufacturer Part Number: LTC1628CG-PG
• Description: IC REG SW 2PHASE STEPDOWN 28SSOP
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC1628CG-PG

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: Adj to 0.8V
• Current - Output: 3A
• Frequency - Switching: 220kHz
• Voltage - Input: 3.5 ~ 30 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
LTC1628/LTC1628-PG
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to I
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the I
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response . Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
The I
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80% of
24
TH
OUT
OUT
series R
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
generating the feedback error signal that
C
-C
LOAD
U
C
OUT
filter sets the dominant pole-zero
(ESR), where ESR is the effective
. I
U
LOAD
also begins to charge or
W
TH
pin not only allows
OUT
shifts by an
U
TH
full-load current having a rise time of 1 s to 10 s will
produce output voltage and I
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the I
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R
increased by decreasing C
factor that C
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance.
A second, more severe transient is caused by switching in
loads with large (>1 F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
should be controlled so that the load rise time is limited to
approximately 25 • C
require a 250 s rise time, limiting the charging current to
about 200mA.
LOAD
OUT
to C
, causing a rapid drop in V
OUT
C
C
is decreased, the zero frequency will be kept
and the bandwidth of the loop will be
is greater than1:50, the switch rise time
LOAD
C
. Thus a 10 F capacitor would
. If R
TH
TH
C
pin signal which is in the
is increased by the same
pin waveforms that will
OUT
. No regulator can
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