LT1738EG#TR Linear Technology, LT1738EG#TR Datasheet - Page 14

• Manufacturer Part Number: LT1738EG#TR
• Description: IC DC/DC CONTRLR LOW NOIS 20SSOP
• Manufacturer: Linear Technology
• Type: Step-Up (Boost), Cuk, Flybackr

Specifications of LT1738EG#TR

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 5 ~ 100 V
• Frequency - Switching: 20kHz ~ 250kHz
• Voltage - Input: 2.55 ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output: -
• Power - Output: -
• Other names: LT1738EGTR

APPLICATIO S I FOR ATIO
LT1738
most of the control circuitry of the regulator. Note after the
control circuitry powers on, gate driver activity will depend
on the voltage of V
As the SHDN pin enables the internal regulator a 24 A
current will be sourced from the pin that can provide
hysteresis for undervoltage lockout. This hysteresis can
be used to prevent part shutdown due to input voltage sag
from an initial high current draw.
In addition to the current hysteresis, there is also approxi-
mately 100mV of voltage hysteresis on the SHDN pin.
When the SHDN pin is greater than 2.2V, the hysteretic
current from the part will be reduced to essentially zero.
If a resistor divider is used to set the turn on threshold then
the resistors are determined by the following equations:
Reworking these equations yields:
So if we wanted to turn on at 20V with 2V of hysteresis:
Resistor values could be altered further by adding zeners
in the divider string. A resistor in series with SHDN pin
could further change hysteresis without changing turn on
voltage.
14
RA
RB
RA
RB
V
V
ON
HYST
2
2
24
V
V
V
V
RA RB
HYST
HYST
RA
• .
• .
1 39
1 39
RB
24
A
I
SHDN
•
•
•
•
V
V
V
V
20
A
I
RA RB
IN
SHDN
SHDN
SHDN
U
V
• .
•
V
with respect to the voltage on GCL.
SHDN
1 39
•
20
20
V
V
ON
SHDN
•
V
V
1 39
U
V
V
.
• .
• .
V
V
SHDN
0 1
0 1
ON
ON
V
I
V
SHDN
SHDN
V
V
•
•
V
V
1 75
W
23 4
SHDN
SHDN
.
.
k
k
RA
RB
V
IN
SHDN
U
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier
(V
Referring to Figure 5, the main pole is formed by capacitor
C
(approximately 400k ). The series resistor R
“zero” which improves loop stability and transient re-
sponse. A second capacitor C
size of the main compensation capacitor, is sometimes
used to reduce the switching frequency ripple on the V
pin. V
attenuated by the output divider and multiplied by the error
amplifier. Without the second capacitor, V
where V
gm = Error amplifier transconductance
R
V
To prevent irregular switching, V
kept below 50mV
maximum output load current and will also be increased if
poor quality (high ESR) output capacitors are used. The
addition of a 0.0047 F capacitor for C
switching frequency ripple to only a few millivolts. A low
value for R
margin may be inadequate.
VC
OUT
VC
C
V
pin).
CPINRIPPLE
= Series resistor on V
and the output impedance of the error amplifier
= DC output voltage
C
RIPPLE
pin ripple is caused by output voltage ripple
VC
will also reduce V
= Output ripple (V
0.01 F
P-P
1 25
C
.
VC
R
VC
2k
. Worst-case V
•
V
Figure 5
RIPPLE
C
V
pin
OUT
VC2
C
C
4.7nF
pin ripple, but loop phase
VC2
•
P-P
, typically one-tenth the
gm R
C
V
C
pin ripple should be
C
1738 F05
)
PIN
•
pin ripple occurs at
VC
VC2
C
pin ripple is:
pin reduces
VC
creates a
1738fa
C