LTC3701EGN#TR Linear Technology, LTC3701EGN#TR Datasheet - Page 5

• Manufacturer Part Number: LTC3701EGN#TR
• Description: IC DC/DC CNTRLR STPDN DUAL16SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3701EGN#TR

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 10 V
• Current - Output: 1A
• Frequency - Switching: 550kHz
• Voltage - Input: 2.5 ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Other names: LTC3701EGNTR

PI FU CTIO S
SENSE1
Differential Current Comparators.
I
two functions. Each pin serves as the error amplifier
compensation point as well as the run control input for the
respective controller. Forcing one pin below 0.35V causes
the functions associated with that controller to be shut
down. Forcing both I
device to be shut down. Nominal operating voltage range
on these pins is from 0.7V to 1.9V.
V
feedback voltage for each controller from an external
resistive divider across the output.
SGND (Pin 4): Signal Ground.
PLLLPF (Pin 7): Serves as the lowpass filter point for the
PLL and as the voltage control input to the internal
oscillator. Normally, a series RC is connected between this
pin and ground when synchronizing to an external clock.
Nominal voltage range is from 0V to 2.4V. Frequency can
be set by forcing this pin with a voltage. Tying this pin to
GND selects 300kHz. Tying to V
selects 750kHz. Floating this pin selects 550kHz opera-
tion.
SENSE2
Inputs to the Differential Current Comparators. These pins
also power the gate drivers.
TH
FB1
/RUN1, I
U
, V
FB2
–
+
, SENSE2
(PV
U
(Pins 3, 5): Each receives the remotely sensed
TH
IN2
/RUN2 (Pins 2, 6): These pins each serve
), SENSE1
–
U
TH/RUN
(Pins 1, 8): The (–) Inputs to the
+
pins below 0.35V causes the
(PV
IN1
IN
) (Pins 9, 16): The (+)
or a voltage
2.4V
EXTCLK/MODE (Pin 10): External Clock Input. Applying a
clock to this pin causes the internal oscillator to phase-
lock to the external clock (nominal lock frequency range
between 300kHz and 750kHz). This also disables Burst
Mode operation but allows pulse-skipping at low load
currents.
Forcing this pin high enables Burst Mode operation.
Forcing this pin low enables pulse-skipping mode. In
these cases, the frequency of the internal oscillator is set
by the voltage on the PLLLPF pin. If the PLLLPF voltage is
not set externally, the frequency internally defaults to
550kHz.
PGOOD (Pin 11): Power Good Output Voltage Monitor
Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V
within 8% of its nominal set point. PGOOD is pulled low
when channel 1 or both channels are shut down. When
channel 2 is shut down and channel 1 enabled, the
PGOOD output indicates the state of V
PGATE2, PGATE1 (Pins 12, 14): Gate Drivers for the
External P-Channel MOSFETs. These pins swing from 0 to
SENSE
PGND (Pin 13): Ground Pin for Gate Drivers.
V
powers the entire chip except for the gate drivers.
IN
(Pin 15): Chip Signal Power Supply Input. This pin
+
(PV
IN
).
FB1
LTC3701
FB1
only.
, V
FB2
) is not
3701fa
5