LTC3701EGN#TR Linear Technology, LTC3701EGN#TR Datasheet - Page 15

• Manufacturer Part Number: LTC3701EGN#TR
• Description: IC DC/DC CNTRLR STPDN DUAL16SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck)r

Specifications of LTC3701EGN#TR

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 2
• Voltage - Output: 0.8 ~ 10 V
• Current - Output: 1A
• Frequency - Switching: 550kHz
• Voltage - Input: 2.5 ~ 10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Other names: LTC3701EGNTR

APPLICATIO S I FOR ATIO
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ( I
resistance of
charge C
regulator loop then returns V
During this recovery time, V
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The I
the dominant pole-zero loop compensation. The I
nal components shown in the Figure 1 circuit will provide
an adequate starting point for most applications. The
values can be modified slightly (from 0.2 to 5 times their
suggested values) to optimize transient response once the
final PC layout is done and the particular output capacitor
type and value have been determined. The output capaci-
tors need to be decided upon because the various types
and values determine the loop feedback factor gain and
phase. An output current pulse of 20% to 100% of full load
current having a rise time of 1 s to 10 s will produce
output voltage and I
of the overall loop stability. The gain of the loop will be
increased by increasing R
will be increased by decreasing C
settling behavior is related to the stability of the closed-
loop system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1 F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
TH
series R
OUT
LOAD
, which generates a feedback error signal. The
COUT
C
)(ESR), where ESR is the effective series
-C
. I
TH
U
C
OUT
filter (see Functional Diagram) sets
pin waveforms that will give a sense
LOAD
immediately shifts by an amount
C
U
, and the bandwidth of the loop
OUT
also begins to charge or dis-
OUT
can be monitored for over-
to its steady-state value.
C
W
. The output voltage
U
TH
exter-
with C
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
Thus a 10 F capacitor would require a 250 s rise time,
limiting the charging current to about 200mA.
Minimum On-Time Considerations
Minimum on-time, t
time that the LTC3701 is capable of turning the top
MOSFET on and then off. It is determined by internal
timing delays and the gate charge required to turn on the
top MOSFET. The minimum on-time for the LTC3701 is
about 250ns. Low duty cycle and high frequency applica-
tions may approach this minimum on-time limit and care
should be taken to ensure that:
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC3701 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3701. These items are illustrated graphically in the
layout diagram of Figure 10. Figure 11 illustrates the
current waveforms present in the various branches of the
2-phase regulators. Check the following in your layout:
1) Are the sense resistors and P-channel MOSFETs for the
two channels located within 1cm of each other with a
common connection at C
input decoupling for the two channels as it can cause a
large resonant loop.
t
ON MIN
OUT
(
, causing a rapid drop in V
)
f V
V
•
OUT
IN
ON(MIN)
IN
? Do not attempt to split the
, is the smallest amount of
OUT
. No regulator can
LTC3701
15
LOAD
3701fa
).