LTC3407EDD-3#PBF Linear Technology, LTC3407EDD-3#PBF Datasheet - Page 10

• Manufacturer Part Number: LTC3407EDD-3#PBF
• Description: IC REG DC/DC DUAL STEPDOWN 10DFN
• Manufacturer: Linear Technology
• Type: Step-Down (Buck)r

Specifications of LTC3407EDD-3#PBF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 2
• Voltage - Output: 0.6 ~ 5 V
• Current - Output: 1A
• Frequency - Switching: 1.5MHz
• Voltage - Input: 2.5 ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

APPLICATIONS INFORMATION
LTC3407-3
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfi ll a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
the output capacitor size. Typically, 3-4 cycles are required
to respond to a load step, but only in the fi rst cycle does
the output drop linearly. The output droop, V
usually about 2-3 times the linear drop of the fi rst cycle.
Thus, a good place to start is with the output capacitor
size of approximately:
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output volt-
ages are above –8.5% of regulation, a timer is started which
releases POR after 2
delay can be signifi cantly longer in Burst Mode operation
with low load currents, since the clock cycles only occur
during a burst and there could be milliseconds of time
between bursts. This can be bypassed by tying the POR
output to the MODE/SYNC input, to force pulse-skipping
mode during a reset. In addition, if the output voltage
faults during Burst Mode sleep, POR could have a slight
delay for an undervoltage output condition and may not
respond to an overvoltage output. This can be avoided by
using pulse-skipping mode instead. When either channel
is shut down, the POR output is pulled low, since one or
both of the channels are not in regulation.
Mode Selection & Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connect-
10
C
OUT
≈ 2.5
f
O
• V
ΔI
OUT
DROOP
18
clock cycles (about 117ms). This
DROOP
, is
ing this pin to V
provides the best low current effi ciency at the cost of a
higher output voltage ripple. Connecting this pin to ground
selects pulse-skipping mode, which provides the lowest
output ripple, at the cost of low current effi ciency.
The LTC3407-3 can also be synchronized to an external
2.25MHz clock signal (such as the SW pin on another
LTC3407-3) by the MODE/SYNC pin. During synchro-
nization, the mode is set to pulse-skipping and the top
switch turn-on is synchronized to the rising edge of the
external clock.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
equal to ΔI
resistance of C
charge C
regulator to return V
this recovery time, V
ringing that would indicate a stability problem. The initial
output voltage step may not be within the bandwidth of the
feedback loop, so the standard second-order overshoot/DC
ratio cannot be used to determine phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a re-
view of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifi cally for this purpose and usually incorporates cur-
rent limiting, short-circuit protection, and soft-starting.
Hot Swap is a trademark of Linear Technology Corporation.
OUT
OUT
LOAD
, generating a feedback error signal used by the
, causing a rapid drop in V
OUT
IN
• ESR, where ESR is the effective series
. ΔI
enables Burst Mode operation, which
OUT
OUT
OUT
LOAD
can be monitored for overshoot or
immediately shifts by an amount
to its steady-state value. During
also begins to charge or dis-
OUT
. No regulator
34073fb