LTC1876EG#PBF Linear Technology, LTC1876EG#PBF Datasheet - Page 21

• Manufacturer Part Number: LTC1876EG#PBF
• Description: IC CTLR/REG STEP UP/DOWN 36SSOP
• Manufacturer: Linear Technology
• Series: PolyPhase®r
• Type: Step-Down (Buck), Step-Up (Boost)r

Specifications of LTC1876EG#PBF

• Internal Switch(s): No
• Synchronous Rectifier: Yes
• Number Of Outputs: 3
• Voltage - Output: Adj to 34V
• Current - Output: 1A
• Frequency - Switching: 140kHz ~ 340kHz
• Voltage - Input: 3.5 ~ 36 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-SSOP
• Primary Input Voltage: 36V
• No. Of Outputs: 3
• Output Voltage: 36V
• Output Current: 25A
• No. Of Pins: 36
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

APPLICATIO S I FOR ATIO
Soft-Start/Run Function
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC1876 step-down controllers. Soft-start re-
duces the input power source’s surge currents by gradu-
ally increasing the controller’s current limit (proportional
to V
sequencing.
An internal 1.2 A current source charges up the C
capacitor
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.3V
to 3.0V, the internal current limit is increased from 25mV/
R
up slowly, taking an additional 1.2s/ F to reach full cur-
rent. The output current thus ramps up slowly, reducing
the starting surge current required from the input power
supply. If RUN/SS has been pulled all the way to ground
there is a delay before starting of approximately:
By pulling both RUN/SS pins below 1.0V and/or pulling the
STBYMD pin below 0.2V, the controllers are put into low
current shutdown (I
driven directly from logic as shown in Figure 7. Diode D1
in Figure 7 reduces the start delay but allows C
up slowly providing the soft-start function. Each RUN/SS
pin has an internal 6V Zener clamp (See Functional Dia-
gram).
SENSE
t
t
DELAY
IRAMP
ITH
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
3.3V OR 5V
). This pin can also be used for power supply
to 75mV/R
.
When the voltage on RUN/SS1 (RUN/SS2)
1 2
3
1 5
Figure 7. RUN/SS Pin Interfacing
.
V
D1
1 2
.
.
(a)
V
A
V
1 5
SENSE
IN
U
C
.
A
Q
R
SS
SS
V
= 20 A). The RUN/SS pins can be
*
RUN/SS
C
. The output current limit ramps
SS
U
1 25
C
.
SS
1 25
s
.
/
W
s
F C
/
INTV
F C
SS
CC
R
SS
SS
(b)
*
SS
U
RUN/SS
to ramp
1876 F07
C
SS
SS
Fault Conditions: Overcurrent Latchoff
The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS capacitor, C
limit the inrush current of the controller. After the control-
ler has been started and been given adequate time to
charge up the output capacitor and provide full load
current, the RUN/SS capacitor is used for a short-circuit
timer. If the regulator’s output voltage falls to less than
70% of its nominal value after C
begins discharging on the assumption that the output is in
an overcurrent condition. If the condition lasts for a long
enough period as determined by the size of the C
specified discharge current, the controller will be shut
down until the RUN/SS pin voltage is recycled. If the
overload occurs during start-up, the time can be approxi-
mated by:
If the overload occurs after start-up the voltage on C
begin discharging from the zener clamp voltage:
If an overload occurs on one channel, it will also latch off
the other channel. This built-in overcurrent latchoff can be
overridden by providing a pull-up resistor to the RUN/SS
pin as shown in Figure 7. This resistance shortens the soft-
start period and prevents the discharge of the RUN/SS
capacitor during an over current condition. Tying this pull-
up resistor to V
latchoff. Diode-connecting this pull-up resistor to INTV
as in Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTV
from preventing controller start-up.
Why should you defeat overcurrent latchoff? During the
prototype stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off. Defeating this feature will easily allow trouble-
shooting of the circuit and PC layout. The internal short-
circuit and foldback current limiting still remains active,
thereby protecting the power supply system from failure.
After the design is complete, a decision can be made
whether to enable the latchoff feature.
T
= 2.7 • 10
T
LO1
LO2
[C
[C
SS
SS
6
(C
(4.1 – 1.5 + 4.1 – 3.5)]/(1.2 A)
(6 – 3.5)]/(1.2 A) = 2.1 • 10
SS
IN
)
as in Figure 7a, defeats overcurrent
SS
, is used initially to turn on and
SS
reaches 4.1V, C
LTC1876
6
(C
CC
SS
SS
21
loading
and the
)
SS
1876fa
will
CC
SS
,