ISL9106IRZ-T Intersil, ISL9106IRZ-T Datasheet - Page 10

• Manufacturer Part Number: ISL9106IRZ-T
• Description: IC REG SYNC BUCK 1.2A 10-DFN
• Manufacturer: Intersil
• Type: Step-Down (Buck)r

Specifications of ISL9106IRZ-T

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 5.5 V
• Current - Output: 1.2A
• Frequency - Switching: 1.6MHz
• Voltage - Input: 2.7 ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-DFN
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -
• Other names: ISL9106IRZ-T

The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage control loop. The
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
discussed separately in “Soft-Start-Up” on page 11. The
EAMP is a transconductance amplifier, which converts the
voltage error signal to a current output. The voltage loop is
internally compensated by a RC network. The maximum
EAMP voltage output is precisely clamped to the bandgap
voltage.
Skip Mode
With the MODE pin connected to logic high, ISL9106 enters
a pulse-skipping mode at light load to minimize the switching
loss by reducing the switching frequency. Figure 26
illustrates the skip mode operation. A zero-cross sensing
circuit (as shown in Figure 24) monitors the N-Channel
MOSFET current for zero crossing. When it is detected to
cross zero for 8 consecutive cycles, the regulator enters the
skip mode. During the 8 consecutive cycles, the inductor
current could be negative. The counter is reset to zero when
the sensed N-Channel MOSFET current does not cross zero
during any cycle within the 8 consecutive cycles.
v
EAMP
v
v
CSA
OUT
d
i
FIGURE 25. PWM OPERATION WAVEFORMS
L
CLOCK
V
OUT
I
L
0
10
8 CYCLES
FIGURE 26. SKIP MODE OPERATION WAVEFORMS
20% PEAK CURRENT LIMIT
1.015*V
ISL9106
OUT_NOMINAL
V
OUT_NOMINAL
Once ISL9106 enters the skip mode, the pulse modulation
starts being controlled by the SKIP comparator shown in
Figure 24. Each pulse cycle is still synchronized by the PWM
clock. The P-Channel MOSFET is turned on at the rising
edge of clock and turned off when its current reaches 20% of
the peak current limit. As the average inductor current in
each cycle is higher than the average current of the load, the
output voltage rises cycle over cycle. When the output
voltage reaches 1.5% above its nominal voltage, the P-
Channel MOSFET is turned off immediately and the inductor
current is fully discharged to zero and stays at zero. The
output voltage reduces gradually due to the load current
discharging the output capacitor. When the output voltage
drops to the nominal voltage, the P-Channel MOSFET will
be turned on again, repeating the previous operations.
The regulator resumes normal PWM mode operation when
the output voltage is sensed to drop below 1.5% of its
nominal voltage value.
Enable
The enable (EN) pin allows user to enable or disable the
converter for purposes such as power-up sequencing. With
EN pin pulled to high, the converter is enabled and the
internal reference circuit wakes up first and then the soft
start-up begins. When EN pin is pulled to logic low, the
converter is disabled, the P-Channel MOSFET is turned off
immediately and the output capacitor is discharged through
internal discharge path.
Power Good
The ISL9106 offers a power-good (PG) signal. When the
output voltage is not within the power-good window, the PG
pin outputs an open-drain low signal. When the output
voltage is within the power-good window, an internal power-
good signal is issued to turn off the open-drain MOSFET so
that PG pin can be externally pulled to high. The rising edge
of the PG output is delayed by 215ms (typical) from the time
the power-good signal is issued.
June 29, 2007
FN6509.0