BD9775FV-E2 Rohm Semiconductor, BD9775FV-E2 Datasheet - Page 10

IC REG SW STEP DOWN HE 28-SSOP

BD9775FV-E2

Manufacturer Part Number
BD9775FV-E2
Description
IC REG SW STEP DOWN HE 28-SSOP
Manufacturer
Rohm Semiconductor
Type
Step-Down (Buck)r
Datasheets

Specifications of BD9775FV-E2

Internal Switch(s)
No
Synchronous Rectifier
Yes
Number Of Outputs
2
Current - Output
400mA
Frequency - Switching
100kHz
Voltage - Input
6 ~ 30 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Power - Output
640mW
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
BD9775FV-E2TR
(8) Method for determining phase compensation
(7) Setting over current detection values
There are 2 current limit function (ON/OFF control type and OFF latch type) toggled by LOFF pin.
・LOFF=L (0<LOFF<1V): Off Latch Type Current Limit
・LOFF=H (1<LOFF<VREG5): ON/OFF Control Type Current Limit
When the current goes beyond the threshold value, the current can be limited by reducing the ON Duty Cycle. When the load
goes back to the normal operation, the output voltage also becomes back on to the specific level.
The output becomes OFF and latched when SS=H and, current limit operation, and the output voltage is less than or equal
to 70% of Vo. The OFF latch is deactivated by re-inputting EN signal or VCC control input (switch OFF and ON once more).
The current limit value(ILimit)is determined by the resistance of the RCL established between CL and VCCCL.
Conditions for application stability
Feedback stability conditions are as follows:
more than 1/10 the switching frequency. In summary, target characteristics for application stability are:
Stability conditions mandate a relatively higher switching frequency, in order to limit GBW enough to increase response.
The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay
(-180°) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the
application.
GBW (the frequency at gain 1) is determined by the phase compensation capacitor connected to the error amp. Thus, a larger
capacitor will serve to lower GBW if desired.
Additionally, in DC/DC applications, sampling is based on the switching frequency; therefore, overall GBW may be set at no
VCCCL
① General use integrator (low-pass filter) ② Integrator open loop characteristics
Feedback
・When gain is 1 (0dB) and phase shift is 150° or less (i.e., phase margin is at least 30°):
・Phase shift of 150° or less (i.e., phase margin of 30° or more) with gain of 1 (0dB)
・GBW (i.e., gain 0dB frequency) no more than 1/10 the switching frequency.
The error amp is provided with phase compensation similar to that depicted in figures ① and ② above and thus serves
as the system’s low-pass filter.
In DC/DC converter applications, R is established parallel to the feedback resistance.
a dual-output high-frequency step-down switching regulator is required
CL
R
VIN
RCL
Fig-23
Fig-26
FB
I
L
L
Vo
A
C
Vo
(OFF Latch
LOFF=L
COMP
Fig-25
I
L
Phase
[deg]
Gain
[dB]
The current limit value
-180
- 1 8 0
-90
1 8 0
- 9 0
0
9 0
A
0
0
Io
Phase margin
Over current detection point
LOFF=H
10/29
Fig-24
Vo×70%
(a)
-90°
Fig-27
-20dB/decade
GBW(b)
-180°
ILimit =
point (a) fa =
point (b) fa = GBW
90m
RCL
2πRCA
[A]・・・(13)
1
2πRC
1
1.25[Hz]
[Hz]

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