ADP3209JCPZ-RL ON Semiconductor, ADP3209JCPZ-RL Datasheet - Page 8

• Manufacturer Part Number: ADP3209JCPZ-RL
• Description: IC CTRLR BUCK 5BIT GMCH 32LFCSP
• Manufacturer: ON Semiconductor

Specifications of ADP3209JCPZ-RL

• Applications: Controller, Power Supplies for Next-Generation Intel Processors
• Voltage - Input: 4.5 ~ 5.5 V
• Number Of Outputs: 1
• Voltage - Output: 0.4 ~ 1.25 V
• Operating Temperature: 0°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Output Voltage: 0.4 V to 1.25 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADP3209JCPZ-RLTR

Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Mnemonic
FBRTN
FB
COMP
SS
ST
PMON
PMONFS
CLIM
LLINE
CSCOMP
CSREF
CSFB
RAMP
VRPM
RPM
RT
GND
PGND
DRVL
PVCC
Description
Feedback Return Input/Output. This pin remotely senses the GMCH voltage. It is also used as the
ground return for the VID DAC and the voltage error amplifier blocks.
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Soft Start and Latch-Off Delay Setting Input/Output. An external capacitor from this pin to GND sets
the soft start ramp-up time and the current limit latch-off delay ramp-down time.
Soft Transient Slew Rate Timing Input/Output. A capacitor from this pin to GND sets the slew rate of
the output voltage when it transitions from one VID setting to another.
Power Monitor Output. Open-drain output. A pull-up resistor from PMON to CSREF provides a duty
cycle–modulated power output signal. An external RC network can be used to convert the digital
signal stream to an averaged power analog output voltage.
Power Monitor Full-Scale Setting Input/Output. A resistor from this pin to GND sets the full-scale
value of the PMON output signal.
Current Limit Setting Input/Output. An external resistor from this pin to GND sets the current limit
threshold of the converter.
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP can be tied to this pin to set the load line slope.
Current Sense Amplifier Output and Frequency Compensation Point.
Current Sense Reference Input. This pin must be connected to the opposite side of the output inductor.
Noninverting Input of the Current Sense Amplifier. The combination of a resistor from the switch
node to this pin and the feedback network from this pin to the CSCOMP pin sets the gain of the
current sense amplifier.
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this
pin sets the slope of the internal PWM stabilizing ramp.
RPM Mode Reference Voltage Output.
Ramp Pulse Modulation Current Source Output. A resistor between this pin and VRPM sets the RPM
comparator upper threshold.
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM
oscillator frequency.
Analog and Digital Signal Ground.
Low-Side Driver Power Ground. This pin should be connected close to the source of the lower MOSFET(s).
Low-Side Gate Drive Output.
Power Supply Input/Output of Low-Side Gate Driver.
PMONFS
FBRTN
COMP
PMON
CLIM
Rev. 2 | Page 8 of 32 | www.onsemi.com
FB
SS
ST
Figure 3. LFCSP Pin Configuration
1
2
3
4
5
6
7
8
(Not to Scale)
ADP3209
PIN 1
INDICATOR
TOP VIEW
24 VCC
23 BST
22 DRVH
21 SW
20 PVCC
19 DRVL
18 PGND
17 GND