ISL6568CR-T Intersil, ISL6568CR-T Datasheet - Page 25

• Manufacturer Part Number: ISL6568CR-T
• Description: IC CTRLR PWM BUCK 2PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6568CR-T

• Applications: Controller, Intel VRM9, VRM10, and AMD Hammer Applications
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (See Interleaving and
Equation 2), a voltage develops across the bulk capacitor
ESR equal to I
are selected, the maximum allowable ripple voltage,
V
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
∆V
Equation 32 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 33
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in MOSFETs, and they establish the upper limit for
the switching frequency. The lower limit is established by the
requirement for fast transient response and small output-
voltage ripple as outlined in Output Filter Design. Choose the
lowest switching frequency that allows the regulator to meet
the transient-response requirements.
L
L
L
PP(MAX)
≤
≤
≥
MAX
2 N C V
--------------------------------- ∆V
(
--------------------------------- - ∆V
(
1.25
ESR
⋅
(
(
. This places an upper limit on inductance.
∆I
∆I
⋅
) N C
)
⋅
, determines the lower limit on the inductance.
)
)
2
2


----------------------------------------------------------- -
⋅
V
⋅
IN
O
f
S
C,PP
V
–
IN
N V
MAX
MAX
V
(ESR). Thus, once the output capacitors
OUT
PP MAX
(
–
–
 V

(
(
∆I ESR
∆I ESR
OUT
)
⋅
⋅
25
)
)


V
IN
–
V
O


(EQ. 32)
(EQ. 33)
(EQ. 31)
ISL6568
Switching frequency is determined by the selection of the
frequency-setting resistor, R
are provided to assist in selecting the correct value for R
R
Input Capacitor Selection
The input capacitors are responsible for sourcing the ac
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the ac component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
For a two-phase design, use Figure 22 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (I
of the peak-to-peak inductor current (I
bulk capacitor with a ripple current rating which will minimize
T
FIGURE 22. NORMALIZED INPUT-CAPACITOR RMS
=
1000
0.3
0.2
0.1
100
0
10
10
0
[
10.61 1.035
10
FIGURE 21. R
I
I
I
L,PP
L,PP
L,PP
–
CURRENT FOR 2-PHASE CONVERTER
= 0
= 0.5 I
= 0.75 I
0.2
log
O
SWITCHING FREQUENCY (kHz)
O
( )
T
f
100
S
DUTY CYCLE (V
vs SWITCHING FREQUENCY
]
0.4
T
. Figure 21 and Equation 34
0.6
1000
IN/
L,PP
V
O
)
) to I
O
), and the ratio
0.8
O
. Select a
March 9, 2006
10000
(EQ. 34)
FN9187.4
T
1.0
.