ISL6568CR-T Intersil, ISL6568CR-T Datasheet - Page 17

• Manufacturer Part Number: ISL6568CR-T
• Description: IC CTRLR PWM BUCK 2PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL6568CR-T

• Applications: Controller, Intel VRM9, VRM10, and AMD Hammer Applications
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.84 ~ 1.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

running at f
voltage change is about 100µs, as calculated using the
following equation.
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V trip point for a
forward/reverse current, at which time the UGATE is released
to rise. An auto-zero comparator is used to correct the r
drop in the phase voltage preventing false detection of the
-0.3V phase level during r
case of zero current, the UGATE is released after 35ns delay of
the LGATE dropping below 0.5V. During the phase detection,
the disturbance of LGATE falling transition on the PHASE node
is blanked out to prevent falsely tripping. Once the PHASE is
high, the advanced adaptive shoot-through circuitry monitors
the PHASE and UGATE voltages during a PWM falling edge
and the subsequent UGATE turn-off. If either the UGATE falls
to less than 1.75V above the PHASE or the PHASE falls to less
than +0.8V, the LGATE is released to turn on.
Internal Bootstrap Device
Both integrated drivers feature an internal bootstrap schottky
diode. Simply adding an external capacitor across the BOOT
and PHASE pins completes the bootstrap circuit. The
bootstrap function is also designed to prevent the bootstrap
capacitor from overcharging due to the large negative swing
at the PHASE node. This reduces voltage stress on the boot
to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V and its capacitance value can be
chosen from the following equation:
where Q
at V
control MOSFETs. The ∆V
allowable droop in the rail of the upper gate drive.
t
C
Q
DVID
BOOT_CAP
GATE
GS1
=
=
G1
gate-source voltage and N
---- -
f
1
S
Q
----------------------------------- - N


S
G1
----------------- -
0.0125
is the amount of gate charge per upper MOSFET
∆
= 335kHz to make a 1.1V to 1.5V reference
≥
V
V
VID
------------------------------------- -
∆V
•
GS1
PVCC
BOOT_CAP
Q
+
GATE
1.5
•


DS(ON)
Q1
BOOT_CAP
17
conduction period. In the
Q1
term is defined as the
is the number of
DS(ON)
(EQ. 12)
(EQ. 11)
ISL6568
Gate Drive Voltage Versatility
The ISL6568 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the
ENLL, VCC, PVCC and the VID pins. When the conditions are
met, the controller begins soft-start. Once the output voltage is
within the proper window of operation, the controller asserts
PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state. This forces the drivers to short gate-
to-source of the upper and lower MOSFET’s to assure the
MOSFETs remain off. The following input conditions must be
met before the ISL6566 is released from this shutdown
mode.
1. The bias voltage applied at VCC must reach the internal
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6568 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6568 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications).
1.6
1.4
1.2
0.8
0.6
0.4
0.2
0.0
1.
0.0
20nC
0.1
VOLTAGE
0.2
50nC
Q
GATE
0.3
= 100nC
∆V
0.4
BOOT_CAP
0.5
0.6
(V)
0.7
0.8
March 9, 2006
0.9
FN9187.4
1.0