MAX8720ETX+ Maxim Integrated Products, MAX8720ETX+ Datasheet - Page 28
![IC CNTRL VID STP DWN 36-TQFN](/photos/6/65/66503/36-tqfn_21-0141i_sml.jpg)
MAX8720ETX+
Manufacturer Part Number
MAX8720ETX+
Description
IC CNTRL VID STP DWN 36-TQFN
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX8720ETXT.pdf
(31 pages)
Specifications of MAX8720ETX+
Applications
Controller, CPU GPU
Voltage - Input
2 ~ 28 V
Number Of Outputs
1
Voltage - Output
0.28 ~ 1.85 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
36-TQFN Exposed Pad
Output Voltage
0.275 V to 1.85 V
Input Voltage
2 V to 28 V
Mounting Style
SMD/SMT
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 12). If possible, mount all of the power compo-
nents on the top side of the board, with their ground
terminals flush against one another. Follow these guide-
lines for good PC board layout:
• Keep the high-current paths short, especially at the
• Keep the power traces and load connections short.
Dynamically Adjustable 6-Bit VID
Step-Down Controller
Figure 12. PC Board Layout Example
28
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
______________________________________________________________________________________
GROUND
PC Board Layout Guidelines
ANALOG
QSOP LAYOUT EXAMPLE
CONNECT AGND
AND PGND TO THE
CONTROLLER AT
ONE POINT ONLY
AS SHOWN
CC
V
REF
CC
V
DD
GROUND
POWER
INPUT
POWER STAGE LAYOUT EXAMPLE
C
C
IN
IN
• When trade-offs in trace lengths must be made, it is
• Route high-speed switching nodes (BST, LX, DH, and
OUTPUT
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-
side MOSFET or between the inductor and the out-
put filter capacitor.
DL) away from sensitive analog areas (REF, FB).
GROUND
GROUND
ANALOG
QFN LAYOUT EXAMPLE
CONNECT AGND
AND PGND TO THE
CONTROLLER AT
ONE POINT ONLY
AS SHOWN
GROUND
POWER