ISL6263BHRZ Intersil, ISL6263BHRZ Datasheet - Page 17

• Manufacturer Part Number: ISL6263BHRZ
• Description: IC DC/DC BUCK CTRLR 1PH 32-QFN
• Manufacturer: Intersil

Specifications of ISL6263BHRZ

• Applications: Converter, Intel IMVP-6
• Voltage - Input: 5 ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.41 ~ 1.29 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LGATE, PVCC, and PGND
PGND is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path. The LGATE trace should
be routed in parallel with the trace from the PGND pin. These
two traces should be short, wide, and away from other traces
because of the high peak current and extremely fast dv/dt.
PVCC should be decoupled to PGND with a ceramic
capacitor physically located as close as practical to the IC
pins.
UGATE, BOOT, and PHASE
PHASE is the return path for the entire UGATE high-side
MOSFET gate driver. The layout for these signals require
similar treatment, but to a greater extent, than those for
LGATE, PVCC, and PGND. These signals swing from
approximately VIN to VSS and are more likely to couple into
other signals.
VSEN and RTN
These traces should be laid out as noise sensitive. For
optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor should be laid out away from rapidly rising voltage
nodes, (switching nodes) and other noisy traces. The filter
capacitors C
conjunction with filter resistors R
common mode and differential mode filters as shown in
Figure 8. The noise environment of the application and
actual board layout conditions will drive the extent of filter
complexity. The maximum recommended resistance for
R
interaction with the 50kΩ input resistance of the remote
sense differential amplifier. The physical location of these
resistors is not as critical as the filter capacitors. Typical
capacitance values for C
range between 330pF to 1000pF and should be placed near
the IC.
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notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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FILTER1
FIGURE 13. TYPICAL POWER COMPONENT PLACEMENT
INDUCTOR
HIGH-SIDE
MOSFETS
and R
GROUND
VIAS TO
FILTER1
PLANE
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FILTER2
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
, C
PHASE
For information regarding Intersil Corporation and its products, see www.intersil.com
NODE
VOUT
FILTER2
GND
VIN
FILTER1
is approximately 10Ω to avoid
17
, and C
OUTPUT
CAPACITORS
FILTER1
, C
FILTER2
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
FILTER3
and R
, and C
FILTER2
used in
FILTER3
form
ISL6263B
RBIAS
The resistor R
the ISL6263B using a noise-free current return path to the
VSS pin.
IMON, SOFT, OCSET, V W, COMP, FB, VDIFF,
DROOP, DFB, VO, and VSUM
The traces and components associated with these pins
require close proximity to the IC as well as close proximity to
each other. This section of the converter circuit needs to be
located above the island of analog ground with the
single-point connection to the VSS pin.
Resistor R
Resistor R
between the power ground and the island of analog ground
connected to the VSS pin.
VID<0:4>, AF_EN, PGOOD, and VR_ON
These are logic signals that do not require special attention.
FDE
This logic signal should be treated as noise sensitive and
should be routed away from rapidly rising voltage nodes,
(switching nodes) and other noisy traces.
VIN
The VIN signal should be connected near the drain of the
high-side MOSFET.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the high-side MOSFET and the source of the
low-side MOSFET to suppress turn-off voltage spikes.
S
is preferably located near the boundary
S
RBIAS
should be placed in close proximity to
July 8, 2010
FN6388.3