ISL6336ACRZ Intersil, ISL6336ACRZ Datasheet - Page 18

IC CTRLR PWM 6PHASE BUCK 48-QFN

ISL6336ACRZ

Manufacturer Part Number
ISL6336ACRZ
Description
IC CTRLR PWM 6PHASE BUCK 48-QFN
Manufacturer
Intersil
Datasheet

Specifications of ISL6336ACRZ

Applications
Controller, Intel VR11.1
Voltage - Input
3 ~ 12 V
Number Of Outputs
1
Voltage - Output
0.5 ~ 1.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-VQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6336ACRZ
Manufacturer:
INTERSIL
Quantity:
280
Load-Line Regulation
Some microprocessor manufacturers require a precisely
controlled output resistance. This dependence of the output
voltage on the load current is often termed “droop” or “load
line” regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a direction
which works to achieve the load-line regulation required by
these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from the fast changes of the load-current demand.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 6, a current proportional to the average
current of all active channels, I
load-line regulation resistor R
across R
creating an output voltage droop with a steady-state value
defined in Equation 8.
The regulated output voltage is reduced by the droop voltage
V
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
Where V
programmed offset voltage, I
of the converter, R
V
V
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE
DROOP
DROOP
OUT
1
1
1
1
1
1
1
1
=
. The output voltage as a function of load current is
FB
REF
V
0
0
0
0
0
0
1
1
=
REF
I
TABLE 3. VR11 VID 8-BIT (Continued)
is proportional to the output current, effectively
AVG
is the reference voltage, V
1
1
1
1
1
1
1
1
V
OFS
ISEN
R
FB
0
0
0
1
1
1
1
1
is the sense resistor connected to
I
------------ -
OUT
N
1
1
1
0
0
0
1
1
OUT
18
FB
AVG
----------------- - R
R
. The resulting voltage drop
ISEN
R
is the total output current
, flows from FB through a
X
1
1
1
0
0
0
1
1
OFS
FB
0
1
1
0
0
1
1
1
is the
1
0
1
0
1
0
0
1
ISL6336, ISL6336A
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
OFF
OFF
(EQ. 8)
(EQ. 9)
the ISEN+ pin, and R
active channel number, and R
depending on the sensing method.
Therefore the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
Output-Voltage Offset Programming
The ISL6336, ISL6336A allows the designer to accurately
adjust the offset voltage. When resistor, R
between OFS to VCC, the voltage across it is regulated to
1.6V. This causes a proportional current (I
OFS. If R
regulated to 0.4V, and I
between DAC and REF, R
product (I
These functions are shown in Figure 7.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to set R
For Positive Offset (connect R
For Negative Offset (connect R
R
R
R
LL
OFS
OFS
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
=
=
=
------------
R
N
1.6 R
--------------------------- -
0.4 R
--------------------------- -
FB
OFS
V
V
OFS
1.6V
OFFSET
OFFSET
----------------- -
R
is connected to ground, the voltage across it is
VCC
x R
+
-
REF
REF
R
ISEN
X
OFS
0.4V
E/A
FB
) is equal to the desired offset voltage.
OFS
GND
+
-
is the feedback resistor, N is the
REF
FB
flows out of OFS. A resistor
X
, is selected so that the
OFS
OFS
is the DCR, or R
OFS
ISL6336, ISL6336A
to VCC):
DYNAMIC
to GND):
VID D/A
:
OFS
OFS
, is connected
) to flow into
SENSE
May 28, 2009
DAC
OFS
GND
VCC
OR
(EQ. 10)
(EQ. 12)
(EQ. 11)
FN6504.1
REF
R
R
C
OFS
REF
REF

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