ISL6334DIRZ-T Intersil, ISL6334DIRZ-T Datasheet - Page 18

• Manufacturer Part Number: ISL6334DIRZ-T
• Description: IC CTRLR PWM 4PHASE VR11.1 40QFN
• Manufacturer: Intersil

Specifications of ISL6334DIRZ-T

• Applications: Controller, Intel VR11.1
• Voltage - Input: 3 ~ 12 V
• Number Of Outputs: 1
• Voltage - Output: 0.5 ~ 1.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Soft-Start
ISL6334D based VR has 4 periods during soft-start, as shown
in Figure 9. After VCC, EN_VTT and EN_PWR reach their
POR/enable thresholds, the controller will have a fixed delay
period t
soft-start ramp until the output voltage reaches 1.1V VBOOT
voltage. Then, the controller will regulate the VR voltage at 1.1V
for another fixed period t
reads the VID signals. If the VID code is valid, ISL6334D will
initiate the second soft-start ramp until the voltage reaches the
VID voltage minus offset voltage.
The soft-start time is the sum of the 4 periods, as shown in
Equation 11.
t
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore, the minimum t
During t
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator, which
is defined by the resistor R
second soft-start ramp time t
based on Equations 12 and 13:
t
D1
SS
FIGURE 8. POWER SEQUENCING USING THRESHOLD
is a fixed delay with the typical value as 1.36ms. t
=
t
FAULT LOGIC
D1
D1
CIRCUIT
SOFT-START
D2
ISL6334D INTERNAL CIRCUIT
POR
. After this delay period, the VR will begin first
+
AND
and t
t
D2
SENSITIVE ENABLE (EN) FUNCTION
+
D4
t
D3
, ISL6334D digitally controls the DAC
+
COMPARATOR
t
D4
D3
ENABLE
D3
. At the end of t
SS
is about 86µs.
D2
18
+
-
0.875V
+
0.875V
-
from SS pin to GND. The
and t
D4
EXTERNAL CIRCUIT
VCC
EN_VTT
EN_PWR
D3
can be calculated
period, ISL6334D
100kΩ
9.1kΩ
+12V
(EQ. 11)
D3
is
ISL6334D
For example, when VID is set to 1.5V and the R
100kΩ, the first soft-start ramp time t
second soft-start ramp time t
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t
typical value for t
released, the controller disregards the PSI# input and
always operates in normal CCM PWM mode.
Current Sense Output
The current flowing out of the IMON pin is equal to the
sensed average current inside ISL6334D. In typical
applications, a resistor is placed from the IMON pin to GND
to generate a voltage, which is proportional to the load
current and the resistor value, as shown in Equation 14:
where V
resistor between the IMON pin and GND, I
output current of the converter, R
connected to the ISEN+ pin, N is the active channel number,
and R
either the DCR of the inductor or R
sensing method.
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.11V
under the maximum load current. If the IMON pin voltage is
higher than 1.11V, overcurrent shutdown will be triggered, as
described in “Overcurrent Protection” on page 19.
A small capacitor can be placed between the IMON pin and
GND to reduce the noise impact. If this pin is not used, tie it
to GND.
t
V
t
D2
D4
IMON
=
=
X
1.1xR
----------------------- - μs
(
------------------------------------------------ μs
6.25x25
V
=
is the DC resistance of the current sense element,
IMON
VID
------------------ -
R
6.25x25
FIGURE 9. SOFT-START WAVEFORMS
IOUT
SS
N
–
1.1
is the voltage at the IMON pin, R
(
VOUT, 500mV/DIV
)xR
D5
----------------- - I
R
)
t
ISEN
R
D1
is 85µs. Before the VR_RDY is
SS
X
EN_VTT
VR_RDY
(
LOAD
)
D4
t
D2
500µs/DIV
will be 256µs.
t
ISEN
D3
SENSE
D2
t
D4
is the sense resistor
will be 704µs and the
t
depending on the
LOAD
D5
IOUT
SS
D5
is the total
August 31, 2010
. The
is set at
is the
(EQ. 12)
(EQ. 13)
(EQ. 14)
FN6802.2