ISL6424ERZ Intersil, ISL6424ERZ Datasheet - Page 11

• Manufacturer Part Number: ISL6424ERZ
• Description: IC REG DUAL LNBP TTL-INP 32-QFN
• Manufacturer: Intersil

Specifications of ISL6424ERZ

• Applications: Converter, Satellite Set-Top Box Designs
• Voltage - Input: 8 ~ 14 V
• Number Of Outputs: 2
• Voltage - Output: 13 ~ 18 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Received Data (
The ISL6424 can provide to the master a copy of the system
register information via the I
mode is Master activated by sending the chip address with
R/W bit set to 1. At the following Master generated clock bits,
the ISL6424 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
• Acknowledge the reception, starting in this way the
• Not acknowledge, stopping the read mode
While the whole register is read back by the microprocessor,
the read-only bits OLF1, OLF2, and OTF convey diagnostic
information about the ISL6424.
Power-On I
The I
at power-on. The I
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
I
These bits are read as they were after the last write operation.
Input Logic High, VIH
Input Logic Low, VIL
Input Logic Current, IIL
SCL Clock Frequency
2
DCL
C Electrical Characteristics
transmission of another byte from the ISL6424.
communication.
2
C interface built into the ISL6424 is automatically reset
ISEL1/2
2
PARAMETER
C Interface Reset
2
I
C interface block will receive a Power OK
2
ENT1/2
C
bus READ MODE)
2
11
C bus in read mode. The read
LLC1/2
VSEL1/1
SDA, SCL
SDA, SCL
SDA, SCL;
0.4V < V
TEST CONDITION
TABLE 7. READING SYSTEM REGISTERS
IN
TABLE 8. I
< 4.5V
EN1/2
ISL6424
2
OTF2
C SPECIFICATIONS
0
1
interface will not respond to any I
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the Vcc rises
above UVLO, the POWER OK signal given to the I
interface block will be HIGH, the I
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the Power-
On reset circuit. (I
at the same time as (or later than) all other I
PWM becomes valid).
ADDRESS Pin
Connecting this pin to GND the chip I
0001000, but, it is possible to choose between two different
addresses simply by setting this pin at one of the two fixed
voltage levels as shown in Table 8.
OLF1/2
MINIMUM
0
1
0
“0001000”
“0001001”
V
V
V
ADDR
ADDR
ADDR
TABLE 6. ADDRESS PIN CHARACTERISTICS
T
T
I
I
OUT
OUT
J
J
-1
-2
≤ 130°C, normal operation
> 150°C, power blocks disabled
< I
> I
MAX
MAX
2
C comes up with EN = 0; EN goes HIGH
, normal operation
, overload protection triggered
MINIMUM
TYPICAL
0.7 x V
0.3 x V
100kHz
2.7V
0V
DD
DD
FUNCTION
2
2
C commands and the
C interface becomes
2
TYPICAL
C interface address is
-
-
2
MAXIMUM
C data for that
400kHz
September 13, 2005
10µA
MAXIMUM
2
C
2V
5V
FN9175.3