L6731D STMicroelectronics, L6731D Datasheet - Page 18

• Manufacturer Part Number: L6731D
• Description: IC CTRLR ADJ STPDN SYNC 16-TSSOP
• Manufacturer: STMicroelectronics

Specifications of L6731D

• Applications: Controller, DDR
• Voltage - Input: 1.8 ~ 14 V
• Number Of Outputs: 1
• Voltage - Output: Adjustable down to 0.6V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Output Voltage: 0.6 V to 18 V
• Output Current: 30 A
• Input Voltage: 1.8 V to 14 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Package: HTSSOP16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Application details
6.3
6.4
18/23
For a given inductor value, minimum input voltage, output voltage and maximum load
transient, a maximum ESR and a minimum Cout value can be set. The ESR and Cout
values also affect the static output voltage ripple. In the worst case the output voltage ripple
can be calculated with the following formula:
Equation 6
Usually the voltage drop due to the ESR is the biggest one while the drop due to the
capacitor discharge is almost negligible.
Input capacitors
The input capacitors have to sustain the RMS current flowing through them, that is:
Equation 7
Where D is the duty cycle. The equation reaches its maximum value, I
The losses in worst case are:
Equation 8
Compensation network
The loop is based on a voltage mode control
the internal/external reference voltage and scaled by the external resistor divider. The error
amplifier output V
pulse-width modulated (PWM) with an amplitude of V
is filtered by the output filter. The modulator transfer function is the small signal transfer
function of V
L-C
Gain of the modulator is simply the input voltage V
voltage: V
OUT
resonance and a zero at FESR depending on the output capacitor's ESR. The DC
OSC
OUT
.
/V
COMP
COMP
. This function has a double pole at frequency F
is then compared with the oscillator triangular wave to provide a
∆
Vout
Irms
P
=
∆
=
=
I
ESR
L
Iout
⋅
(
ESR
⋅
(Figure
0 (
⋅
5 .
D
+
⋅
8
IN
⋅
Iout
1 ( D
⋅
18.). The output voltage is regulated to
divided by the peak-to-peak oscillator
Cout
IN
−
)
at the PHASE node. This waveform
2
1
)
⋅
Fsw
)
OUT
LC
depending on the
/2 with D = 0.5.
L6731D