MAX1778EUG+ Maxim Integrated Products, MAX1778EUG+ Datasheet - Page 30

• Manufacturer Part Number: MAX1778EUG+
• Description: IC DCDC CONV MULTI OUT 24TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1778EUG+

• Applications: Converter, TFT, LCD
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 5
• Voltage - Output: 2.7 ~ 13 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Quad-Output TFT LCD DC-DC
Converters with Buffer
0.8µA (max). For less than 0.5% error due to FBL input
bias current (I
Capacitors are required at the input and output of the
MAX1778/MAX1881/MAX1883/MAX1884 for stable
operation over the full temperature range and with load
currents up to 40mA. Connect a 1µF input bypass
capacitor (C
the source impedance of the input supply. Connect a
ceramic capacitor between LDOOUT and ground,
using the following equation to determine the lowest
value required for stable operation:
For example, with a 5V linear regulator output voltage
and a maximum 40mA load, use at least 4µF of output
capacitance. Applications that experience high-current
load pulses may require more output capacitance.
The ESR of the linear regulator’s output capacitor
(C
put capacitors with an ESR of 0.1Ω or less to ensure
stability and optimum transient response. Surface-
mount ceramic capacitors are good for this purpose.
Place C
lator as possible to minimize the impact of PC board
trace inductance.
For applications where the linear regulator currents
exceed 40mA or where the power dissipation in the IC
needs to be reduced, an external NPN transistor can
be used. In this case, the internal LDO only provides
the necessary base drive while the external NPN tran-
sistor supports the load, so most of the power dissipa-
tion occurs across the external transistor’s collector
and emitter.
Selection of the external NPN transistor is based on
three factors: the package’s power dissipation, the cur-
rent gain (β), and the collector-to-emitter saturation volt-
age (V
should not exceed the transistor’s package rating:
Once the appropriate package type is selected, con-
sider the NPN transistor’s current gain. Since the inter-
nal LDO cannot source more than 40mA (min), the
transistor’s current gain must be high enough at the
lowest collector-to-emitter voltage to support the maxi-
mum output load:
30
LDOOUT
______________________________________________________________________________________
C
CE(SAT)
P
SUPL
LDOOUT
Capacitor Selection and Regulator Stability
=
) affects stability and output noise. Use out-
(
SUPL
V
and C
FBL
COLLECTOR
). First, the maximum power dissipation
), R8 must be less than 8kΩ.
) between SUPL and ground to lower
≥
LDOOUT
0 5
.
ms X
−
as close to the linear regu-
External Pass Transistor
V
⎛
⎜
⎜
⎝
LDO
I
LDOOUT MAX
V
)
LDOOUT
x I
(
LOAD MAX
)
(
⎞
⎟
⎟
⎠
)
For stable operation, place a capacitor (C
a minimum load resistor (R5) at the output of the inter-
nal linear regulator (the base of the external transistor)
to set the dominant pole:
Since the LDO cannot sink current, a minimum pull-
down resistor (R5) is required at the base of the NPN
transistor to sink leakage currents and improve the
high-to-low load-transient response. Under no-load
conditions, leakage currents from the internal pass
transistor supply the output capacitor (C
when the transistor is off. As the leakage currents
increase over temperature, charge may build up on
C
above its set point. Therefore, R5 must sink at least
100µA to guarantee proper regulation. Additionally, the
minimum load current provided by R5 improves the
high-to-low load transients by lowering the impedance
seen by C
if large load transients are expected, select R5 so that
the minimum load current is 10% of the transistor’s
maximum base current:
Alternatively, output capacitance placed on the external
linear regulator’s output (the emitter) adds a second pole
that could destabilize the regulator. A capacitive-divider
from the transistor’s base to the feedback input (C2 and
C3, Figure 7) circumvents this second pole by adding a
pole-zero pair. Furthermore, to minimize excessive over-
shoot, the capacitive-divider’s ratio must be the same as
the resistive-divider’s ratio. Once the output capacitor is
selected, using the following equations to determine the
required capacitive-divider values:
LDOOUT
R
5
C
C
=
2
, making the linear regulator’s output rise
LDOOUT
2
C
x
C
V
I
+
β
LDOOUT
+
LDOOUT MIN
⎛
⎜
⎝
LDO
2
MIN
V
C
C
LDO
3
3
+
≥
≥
after the transient occurs. Therefore,
=
R
(
+
0 7
5
I
C
LOAD MAX
≥
.
R
100
LDO
0 7
3
V
.
)
0 5
R
.
+
V
4
(
=
⎛
⎜
⎝
ms
R
1
40
+
0 1
4
+
⎛
⎜
⎝
mA
.
)
I
V
LOAD MAX
LDO
R
R
=
- 40
⎡
⎢
⎢
⎣
1
4
3
(
β
V
⎞
⎟
⎠
V
MIN
V
LDO
LDO
(
⎞
⎟
⎠
REF
mA
I
LOAD MAX
LDOOUT
+
LDOOUT
)
⎞
⎟
⎠
0 7
(
.
V
), even
)
)
β
) and
MIN