MAX1778EUG+ Maxim Integrated Products, MAX1778EUG+ Datasheet - Page 25

• Manufacturer Part Number: MAX1778EUG+
• Description: IC DCDC CONV MULTI OUT 24TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1778EUG+

• Applications: Converter, TFT, LCD
• Voltage - Input: 2.7 ~ 5.5 V
• Number Of Outputs: 5
• Voltage - Output: 2.7 ~ 13 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

where I
input supply currents for the charge pumps (see
Charge-Pump
Considerations), linear regulator, and VCOM buffer.
The linear regulator generates an output voltage by dis-
sipating power across an internal pass transistor, so
the power dissipation is simply the load current times
the input-to-output voltage differential:
When driving an external transistor, the internal linear
regulator provides the base drive current. Depending
on the external transistor’s current gain (β) and the
maximum load current, the power dissipated by the
internal linear regulator may still be significant:
The charge pumps provide regulated output voltages
by dissipating power in the low-side N-channel MOS-
FET, so they could be modeled as linear regulators fol-
lowed by unregulated charge pumps. Therefore, their
power dissipation is similar to a linear regulator:
where N is the number of charge-pump stages, V
is the diodes’ forward voltage, and V
tive charge-pump diode supply (Figure 4).
The VCOM buffer’s power dissipation depends on the
capacitive load (C
peak voltage change (V
load’s switching rate:
To find the total power dissipated in the device, the
power dissipated by each regulator and the buffer must
be added together:
The maximum allowed power dissipation is 975mW (24-
pin TSSOP) / 879mW (20-pin TSSOP) or:
P
P
NEG
POS
P
LDO INT
MAIN
=
=
P
I
(
I
POS
TOTAL
NEG
P
P
BUF
LDO INT
includes the primary load current and the
)
[
(
[
(
(
=
=
V
V
SUPN
=
SUPP
______________________________________________________________________________________
Input
=
I
I
LDOOUT
LDO
)
LOAD
V
β
P
+
P P LOAD LOAD SUPB
=
STEP UP
-
-
P
-
[
I
NEG
V
P-P
LDO SUPL
2
) being driven, the peak-to-
2
C
SUPL
V
V
-
Power
DIODE
(
DIODE
) across the load, and the
V
(
SUPL
V
+
-
+
f
P
)
POS
)
N
(
N
V
P
-
LDO
LDO INT
-
+
and
-
V
V
SUPD
V
LDOOUT
+
NEG
V
V
(
SUPD
LDO
+
P
BUF
]
)
0 7
is the posi-
Efficiency
)
.
-
Quad-Output TFT LCD DC-DC
V
)
)
V
]
POS
DIODE
]
where T
the controller’s junction and the surrounding air, θ
θ
board, and θ
ed circuit board to the surrounding air.
Adjust the output voltage by connecting a voltage-
divider from the output (VMAIN) to FB to GND (see
Typical Operating Circuit). Select R2 in the 10kΩ to
50kΩ range. Calculate R1 with the following equations:
where V
Inductor selection depends upon the minimum required
inductance value, saturation rating, series resistance, and
size. These factors influence the converter’s efficiency,
maximum output load capability, transient response time,
and output voltage ripple. For most applications, values
between 4.7µH and 22µH work best with the controller’s
switching frequency (Tables 1 and 2).
The inductor value depends on the maximum output
load the application must support, input voltage, output
voltage, and switching frequency. With high inductor
values, the MAX1778/MAX1880–MAX1885 source high-
er output currents, have less output ripple, and enter
continuous conduction operation with lighter loads;
however, the circuit’s transient response time is slower.
On the other hand, low-value inductors respond faster
to transients, remain in discontinuous conduction oper-
ation, and typically offer smaller physical size for a
given series resistance and current rating. The equa-
tions provided here include a constant LIR, which is the
ratio of the peak-to-peak AC inductor current to the
average DC inductor current. For a good compromise
between the size of the inductor, power loss, and out-
put voltage ripple, select an LIR of 0.3 to 0.5. The
inductance value is then given by:
Converters with Buffer
JC
L
) is the thermal resistance of the package to the
MIN
REF
J
=
P
- T
MAX
⎛
⎜
⎝
= 1.25V. V
BA
A
V
R1 = R2 [(V
V
IN MIN
MAIN
is the temperature difference between
= (T
is the thermal resistance from the print-
(
J(MAX
)
⎞
⎟
⎠
MAIN
2
⎛
⎜
⎝
Main Step-Up Converter
V
MAIN
) - T
I
MAIN
MAIN MAX OSC
Design Procedure
may range from V
Output Voltage Selection
A
/ V
) / ( θ
(
-
REF
V
IN MIN
Inductor Selection
)
JB
f
) - 1]
(
+ θ
)
⎞
⎟
⎠
BA
⎛
⎜
⎝
)
LIR
IN
1
to 13V.
⎞
⎟
⎠
JB
η
(or
25