CS5124XD8 ON Semiconductor, CS5124XD8 Datasheet - Page 7

• Manufacturer Part Number: CS5124XD8
• Description: IC CTRLR PWM CURRENT MODE 8-SOIC
• Manufacturer: ON Semiconductor

Specifications of CS5124XD8

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 440kHz
• Duty Cycle: 85%
• Voltage - Supply: 7.6 V ~ 20 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 440kHz
• Output Voltage: - 0.3 V to + 20 V
• Output Current: 200 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 440 KHz
• Operating Supply Voltage: 7.7 V to 20 V
• Maximum Operating Temperature: + 135 C
• Fall Time: 25 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 45 ns
• Synchronous Pin: No
• Topology: Flyback, Forward
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

the Soft−Start error amp is clamped at 2.9 V. During fault
conditions the Soft−Start capacitor is discharged at 10 mA.
Fault Conditions
Thermal Shutdown, V
Threshold. Once a fault is recognized, fault latch F2 is set
and the IC immediately shuts down the output driver and
discharges the Soft−Start capacitor. Soft−Start will begin
only after all faults have been removed and the Soft−Start
capacitor has been discharged to less than 0.275 V. Each
fault will be explained in the following sections.
Under Voltage Lockout (UVLO)
resistive divider between V
up sequence, this pin must be above 2.6 V in order for the IC
to begin normal operation. If the IC is running and this pin
is pulled below 1.8 V, F2 shuts down the output driver and
discharges the Soft−Start capacitor in order to insure proper
startup. If the UVLO pin is pulled high again before the
Soft−Start capacitor discharges, the IC will complete the
Soft−Start discharge and, if no other faults are present, will
immediately restart the power supply. If the UVLO pin stays
low, then it will enter either the low current sleep mode or the
UVLO state depending on the level of the UVLO pin.
Thermal Shutdown
150 C the thermal shutdown circuit sets F2, which shuts
down the output driver and discharges the Soft−Start
capacitor. If no other faults are present the IC will initiate
Soft−Start when the IC junction temperature has been
reduced by 25 C.
V
regulator is running before any switching occurs. This
function does not trip the fault comparator like the other fault
functions. To insure that Soft−Start will occur at low line
conditions the UVLO divider should be set up so that the
V
comparator.
REF(OK)
CC
The CS5124 recognizes the following faults: UVLO off,
The UVLO pin is tied to typically the midpoint of a
If the IC junction temperature exceeds approximately
V
REF(OK)
UVLO comparator turns on before the LINE UVLO
is an internal monitor that insures the internal
REF(OK)
IN
and GROUND. During a start
, and Second Current
http://onsemi.com
7
Second Threshold Comparator
in normal operation is 195 mV, any voltage exceeding this
threshold on the I
PWM cycle is terminated. The 2nd I
I
voltage exceeds the second threshold, F2 is set, the driver
turns off, and the Soft−Start capacitor discharges. After the
Soft−Start capacitor has discharged to less than 0.275 V
Soft−Start will begin. If the fault condition has been
removed the supply will operate normally. If the fault
remains the supply will operate in hiccup mode until the
fault condition is removed.
V
too high. When the regulated output voltage is too high, the
feedback loop will drive V
the output of the V
output driver off.
Oscillator
compensation ramp as well as the pulse for enabling the
output driver.
PWM Comparator and Slope Compensation
ramp that is subtracted from the feedback signal. The PWM
comparator compares peak primary current to a portion of
the difference of the feedback voltage and slope
compensation ramp. The 170 mV/ms slope compensation
ramp is subtracted from the voltage feedback signal
internally. The difference signal is then divided by ten before
the PWM comparator to provide high noise rejection with a
low voltage across the current sense network. The effective
ramp is 21 mV/ms. A 60 mV nominal offset on the positive
input to the PWM comparator allows for operation with the
I
nominal reference provides the bias current to for an
optocoupler connection to the V
SENSE
SENSE
FB
Since the maximum dynamic range of the I
The V
The internally trimmed, 400 kHz provides the slope
The CS5124 provides a fixed internal slope compensation
A 4.3 kW pull−up resistor internally connected to a 5.0 V
Comparator
pin at, or even slightly below GND.
FB
signal with a 275 mV threshold. If the I
comparator detects when the output voltage is
SENSE
FB
comparator will go high and shut the
pin is considered a fault and the
FB
low. If V
FB
pin.
FB
COMP
is less than 0.49 V
compares the
SENSE
SENSE
signal