CS5124XD8 ON Semiconductor, CS5124XD8 Datasheet - Page 6

• Manufacturer Part Number: CS5124XD8
• Description: IC CTRLR PWM CURRENT MODE 8-SOIC
• Manufacturer: ON Semiconductor

Specifications of CS5124XD8

• Pwm Type: Current Mode
• Number Of Outputs: 1
• Frequency - Max: 440kHz
• Duty Cycle: 85%
• Voltage - Supply: 7.6 V ~ 20 V
• Buck: No
• Boost: No
• Flyback: Yes
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: Yes
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 8-SOIC (3.9mm Width)
• Frequency-max: 440kHz
• Output Voltage: - 0.3 V to + 20 V
• Output Current: 200 mA
• Mounting Style: SMD/SMT
• Switching Frequency: 440 KHz
• Operating Supply Voltage: 7.7 V to 20 V
• Maximum Operating Temperature: + 135 C
• Fall Time: 25 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 45 ns
• Synchronous Pin: No
• Topology: Flyback, Forward
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Powering the IC
requires 500 mA of startup current. The CS5124 includes a
line bias pin (BIAS) that can be used to control a series pass
transistor for operation over a wide input voltage. The BIAS
pin will control the gate voltage of an N−channel MOSFET
placed between V
V
shutdown, Line UVLO, and normal operation. To illustrate
how the UVLO pin works; assume that V
application schematic, is ramped up starting at 0 V with the
UVLO pin open. The SS and I
While the UVLO is below 1.8 V, the IC will remain in a low
current sleep mode and the BIAS pin of the CS5124 is
internally clamped to a maximum of 15 V. When the voltage
on the UVLO pin rises to between 1.8 V and 2.6 V the
reference for the V
UVLO
V
BIAS
CC
CC
V
The UVLO pin has three different modes; low power
SS
CC
and UVLO Pins
can be powered directly from a regulated supply and
V
+
150 C/125 C
CC
V
TSHUT
LINE AMP
7.7 V/7.275 V
UVLO COMP
+
−
+
V 1.91 V/1.83 V
L
INE UVLO COMP
(SLEEP) COMP
IN
2.0 V
+
+
−
REMOTE
V
and V
CC
+
−
2.62 V/2.45 V
+
+
−
V
UVLO is enabled and V
V
CC
G2
CC
ENABLE
2.9 R
R
to regulate V
SENSE
V
Soft−Start LATCH
REF
G5
SS COMP
V
CC
= 5.0 V
V
pins also start at 0 V.
SET DOMAIN
S
R
+
IN
275 mV
F2
V
+
−
, as shown in the
REFOK
CC
Q
+
−
at 8.0 V.
THEORY OF OPERATION
+
V
Figure 2. Block Diagram
OSC
RAMP
V5
DIS
http://onsemi.com
V5
REF
CC
REF
10 mA
is
2.90 V
1.32 V
+
2ND
I
COMP
6
V
+
V
PWM COMP
V
regulated to 8.0 V by the BIAS pin, but the IC remains in a
UVLO state and the output driver does not switch. When the
UVLO pin exceeds 2.6 V and the V
GATE pin is released from a low state and can begin
switching based on the comparison of the I
pins. The Soft−Start capacitor begins charging from 0 V at
10 mA. As the capacitor charges, a buffered version of the
capacitor voltage appears on the V
voltage begins to rise. As V
until the supply comes into regulation.
Soft−Start
below the SS pin during normal start up and during restart
after a fault condition. When the CS5124 starts, the
Soft−Start capacitor is charged from a 10 mA source from 0
V to 4.9 V. The V
by −1.32 V until the supply comes into regulation or until
FB
+
−
Soft−Start is accomplished by clamping the V
RESET DOMAIN
+
G3
COMP
BLANK
V
V5
275 mV
REF
+
−
60 mV
+
−
+
R
S
+
V
V
F1
G6
490 mV
Q
FB
170 mV/ms
pin follows the Soft−Start pin offset
BLANKING
1/10
1000 W
G1
FB
rises the duty cycle increases
S
R
SS AMP
G7
F3
CC
+
−
Q
4500 W
FB
pin exceeds 7.7 V, the
pin and the V
DRIVER
V5
SENSE
REF
FB
pin 1.32 V
and V
I
GND
V
GATE
SENSE
FB
FB
FB