ISL6564CR Intersil, ISL6564CR Datasheet - Page 21

• Manufacturer Part Number: ISL6564CR
• Description: IC CTRLR PWM MULTIPHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6564CR

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.7%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

on pages 4 to 7, load current information can be obtained by
measuring the voltage between IOUT to ground when a NTC
network from IOUT pin to the ground is placed. The output
current at IOUT pin is proportional to load current as shown
in Figure 17.
When selecting the equivalent resistor network components
values, it is important to ensure the voltage at IOUT pin not
exceed 2V.
When ISL6564 is operated at single phase mode (both
PWM3 and PWM4 connected to VCC and PWM2
unconnected). The output current at IOUT and IDROOP is
half of the sensed phase current.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multi-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced below. In
addition to this guide, Intersil provides complete reference
designs that include schematics, bills of materials, and
example board layouts for all common microprocessor
applications.
Power Stages
The first step in designing a multi-phase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 15 and 20A. All
surface-mount designs will tend toward the lower end of this
FIGURE 17. VOLTAGE AT IOUT PIN WITH A NTC NETWORK
0A
PLACED BETWEEN IOUT TO GROUND WHEN
LOAD CURRENT CHANGES
V_IOUT, 200mV/DIV
21
50A
100A
ISL6564
current range. If through-hole MOSFETs and inductors can
be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs require
heat sinks and forced air to cool the MOSFETs, inductors
and heat-dissipating surfaces.
MOSFETs
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (r
continuous output current; I
current (see Equation 1); d is the duty cycle (V
L is the per-channel inductance.
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P
P
UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
recovery charge, Q
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
P
P
LOW,2
LOW 1
LOW 2
,
,
.
=
=
r
V
S
DS ON
DS(ON)
D ON
; and the length of dead times, t
(
DS(ON)
(
IN
)
) during switching. Since a substantially
)
f
S
rr
). In Equation 14, I



; and the upper MOSFET r
I
----- -
N
M


losses, a large portion of the upper-
I
----- -



N
M
2
(
+
M
1 d
I
-------- -
, V
PP
–
PP
2
D(ON)
 t

)
is the peak-to-peak inductor
+
d1
I
--------------------------------
L PP
,
+
2
; the switching



12
I
----- -
M
(
N
M
1 d
is the maximum
–
–
I
-------- -
PP
2
)
d1



OUT
December 27, 2004
t
DS(ON)
d2
and t
LOW,1
/V
IN
d2
(EQ. 14)
(EQ. 15)
FN9156.2
); and
, at
and