HIP6018BCB Intersil, HIP6018BCB Datasheet - Page 8

• Manufacturer Part Number: HIP6018BCB
• Description: IC PWM DUAL PWR CONTROL 24-SOIC
• Manufacturer: Intersil

Specifications of HIP6018BCB

• Pwm Type: Voltage Mode
• Number Of Outputs: 3
• Frequency - Max: 215kHz
• Duty Cycle: 100%
• Voltage - Supply: 3.3 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 215kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

and V
generating a fault. Cycling the bias input voltage (+12V
the VCC pin) off then on resets the counter and the fault latch.
Over-Voltage Protection
During operation, a short on the upper PWM MOSFET (Q1)
causes V
over-voltage threshold of 115% (typical) of DACOUT, the
over-voltage comparator trips to set the fault latch and turns
Q2 on as required in order to regulate V
DACOUT. This blows the input fuse and reduces V
The fault latch raises the FAULT pin close to VCC potential.
A separate over-voltage circuit provides protection during
the initial application of power. For voltages on the VCC pin
below the power-on reset (and above ~4V), V
monitored for voltages exceeding 1.26V. Should VSEN1
exceed this level, the lower MOSFET (Q2) is driven on as
needed to regulate V
Over-Current Protection
All outputs are protected against excessive over-currents.
The PWM controller uses the upper MOSFET’s on-
resistance, r
against shorted outputs. The linear regulator monitors the
current of the integrated power device and signals an over-
current condition for currents in excess of 230mA.
Additionally, both the linear regulator and the linear
controller monitor FB2 and FB3 for under-voltage to protect
against excessive currents.
Figures 8 and 9 illustrate the over-current protection with an
overload on OUT1. The overload is applied at T0 and the
current increases through the output inductor (L
T1, the OVER-CURRENT1 comparator trips when the voltage
across Q1 (I
R
capacitor (C
counter.C
with the error amplifiers clamped by soft-start. With OUT1 still
overloaded, the inductor current increases to trip the over-
current comparator. Again, this inhibits all outputs, but the
LUV
OC1
OV
SS
OCSET
0.15V
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
OUT3
4V
. This inhibits all outputs, discharges the soft-start
OUT1
SS
+
-
+
-
to slew up over increased time intervals, without
D
SS
DS(ON)
recharges at T2 and initiates a soft-start cycle
•
) with a 11μA current sink, and increments the
r
to increase. When the output exceeds the
CURRENT
DS(ON)
UP
LATCH
OVER
S
R
to monitor the current for protection
OUT1
Q
) exceeds the level programmed by
POR
to 1.26V.
8
R
COUNTER
S
OUT1
INHIBIT
LATCH
FAULT
S
R
OUT1
OUT1
to 1.15 x
Q
). At time
OUT1
is
VCC
IN
FAULT
on
.
HIP6018B
soft-start voltage continues increasing to 4V before
discharging. The counter increments to 2. The soft-start cycle
repeats at T3 and trips the over-current comparator. The SS
pin voltage increases to 4V at T4 and the counter increments to
3. This sets the fault latch to disable the converter. The fault is
reported on the FAULT pin.
The linear regulator operates in the same way as PWM1 to
over-current faults. Additionally, the linear regulator and
linear controller monitor the feedback pins for an under-
voltage. Should excessive currents cause FB2 or FB3 to fall
below the linear under-voltage threshold, the LUV signal
sets the over-current latch if C
LUV signal during the C
outputs to build above the under-voltage threshold during
normal start-up. Cycling the bias input power off then on
resets the counter and the fault latch.
Resistor R
PWM converter. As shown in Figure 9, the internal 200μA
current sink develops a voltage across R
referenced to V
comparator (OVER-CURRENT1). When the voltage across the
upper MOSFET (V
comparator trips to set the over-current latch. Both V
V
R
MOSFET switching. The over-current function will trip at a peak
inductor current (I
I PEAK =
DS
OCSET
10V
0A
0V
4V
2V
0V
are referenced to V
helps V
I OCSET xR OCSET
------------------------------------------------------ -
OCSET1
FIGURE 8. OVER-CURRENT OPERATION
T0
COUNT
= 1
T1
r DS ON
OVERLOAD
APPLIED
IN
OCSET
. The DRIVE signal enables the over-current
PEAK)
(
DS(ON)
programs the over-current trip level for the
)
SS
IN
determined by:
track the variations of V
T2
) exceeds V
and a small capacitor across
charge interval allows the linear
COUNT
SS
TIME
= 2
REPORTED
is fully charged. Blanking the
FAULT
SET
OCSET
, the over-current
T3
IN
(V
COUNT
SET
due to
= 3
T4
SET
) that is
and