HIP6018BCB Intersil, HIP6018BCB Datasheet - Page 11

• Manufacturer Part Number: HIP6018BCB
• Description: IC PWM DUAL PWR CONTROL 24-SOIC
• Manufacturer: Intersil

Specifications of HIP6018BCB

• Pwm Type: Voltage Mode
• Number Of Outputs: 3
• Frequency - Max: 215kHz
• Duty Cycle: 100%
• Voltage - Supply: 3.3 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-SOIC (7.5mm Width)
• Frequency-max: 215kHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The modulator transfer function is the small-signal transfer
function of V
gain and the output filter, with a double pole break frequency
at F
simply the input voltage, V
oscillator voltage, ΔV
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
internal to the HIP6018B and the impedance networks Z
Z
closed loop transfer function with an acceptable 0dB crossing
frequency (f
the difference between the closed loop phase at f
degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 11. Use these guidelines for
locating the poles and zeros of the compensation network:
F
1. Pick Gain (R2/R1) for desired converter bandwidth
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
2. Place 1
FB
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
LC
Δ
V
. The goal of the compensation network is to provide a
LC
=
OSC
--------------------------------------- -
2π
and a zero at F
×
ST
0dB
ND
ST
ND
OSC
L
OUT
1
ERROR
COMPENSATION DESIGN
O
Zero Below Filter’s Double Pole (~75% F
AMP
Pole at the ESR Zero
) and adequate phase margin. Phase margin is
Zero at Filter’s Double Pole
Pole at Half the Switching Frequency
×
HIP6018B
V
/V
C
E/A
O
COMP
E/A
DETAILED FEEDBACK COMPENSATION
PWM
Z
+
OSC
-
COMP
+
-
FB
C1
. This function is dominated by a DC
ESR
REFERENCE
REFERENCE
.
F
IN
. The DC gain of the modulator is
C2
ESR
+
-
R2
DRIVER
DRIVER
, divided by the peak-to-peak
11
Z
=
IN
---------------------------------------- -
2π
×
Z
FB
ESR
FB
V
IN
PHASE
1
C3
(PARASITIC)
×
Z
R1
C
L
IN
O
O
ESR
0dB
R3
C
V
O
and 180
OUT
LC
IN
V
)
OUT
and
HIP6018B
Compensation Break Frequency Equations
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual modulator gain has a peak due
to the high Q factor of the output filter at F
shown in Figure 12. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
amplifier. The closed loop gain is constructed on the log-log
graph of Figure 12 by adding the modulator gain (in dB) to the
compensation gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
Z
stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
The output capacitors for each output have unique
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output
capacitor to filter the current ripple. The linear regulator is
internally compensated and requires an output capacitor that
meets the stability requirements. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
F
F
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
FB
Z1
Z2
100
-20
-40
-60
80
60
40
20
0
and Z
=
=
-----------------------------------
2π
------------------------------------------------------ -
2π
10
(R
20LOG
2
MODULATOR
×
×
IN
/R
R
(
R1
1
1
to provide a stable, high bandwidth loop. A
2
)
GAIN
100
×
+
1
C1
R3
)
×
1K
F
C3
P2
Z1
F
FREQUENCY (Hz)
LC
F
with the capabilities of the error
Z2
10K
F
P1
F
F
P1
ESR
=
(V
100K
IN
F
------------------------------------------------------ -
2π
20LOG
F
P2
/ΔV
P2
×
OSC
=
R
OPEN LOOP
ERROR AMP GAIN
LC
2
-----------------------------------
2π
1M
)
×
, which is not
1
⎛
⎝
×
--------------------- -
C1
C1 C2
COMPENSATION
R
CLOSED LOOP
1
3
×
+
10M
×
GAIN
C2
GAIN
C3
⎞
⎠