HIP6004ECV Intersil, HIP6004ECV Datasheet - Page 5

• Manufacturer Part Number: HIP6004ECV
• Description: IC CTRLR PWM VOLTAGE MON 20TSSOP
• Manufacturer: Intersil

Specifications of HIP6004ECV

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 100%
• Voltage - Supply: 5 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-TSSOP
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PGND (Pin 16)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
VCC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
RT (Pin 20)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
200kHz switching frequency is increased according to the
following equation:
Conversely, connecting a pull-up resistor (R
V
following equation:
RT pin has a constant voltage of 1.26V typically.
Functional Description
Initialization
The HIP6004E automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the VCC
pin and the input voltage (V
OCSET is equal to V
current protection). The POR function initiates soft-start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, V
and V
exceed the rising VCC threshold before POR initiates operation.
Soft Start
The POR function initiates the soft-start sequence. An internal
10µA current source charges an external capacitor (C
Fs
CC
≈
200kHz
reduces the switching frequency according to the
CC
are equivalent and the +12V power source must
Fs
+
-------------------- -
R
5 x 10
≈
T
(
200kHz
kΩ
IN
6
)
less a fixed voltage drop (see over-
T
) from this pin to GND, the nominal
–
(R
IN
-------------------- -
R
4 x 10
T
T
) on the OCSET pin. The level on
(
to GND)
5
kΩ
7
)
(R
T
to 12V)
T
) from this pin to
SS
) on
IN
HIP6004E
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft-start interval with
C
pin) controls the converter’s output voltage. At t
SS voltage reaches the valley of the oscillator’s triangle wave.
The oscillator’s triangular waveform is compared to the ramping
error amplifier voltage. This generates PHASE pulses of
increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t
output voltage, the clamp on the reference input controls the
output voltage. This is the interval between t
At t
output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within ±10% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
Overcurrent Protection
The overcurrent function protects the converter from a shorted
output by using the upper MOSFET’s on-resistance, r
to monitor the current. This method enhances the converter’s
efficiency and reduces cost by eliminating a current sensing
resistor.
SS
0V
0V
0V
3
= 0.1µF. Initially the clamp on the error amplifier (COMP
the SS voltage exceeds the DACOUT voltage and the
FIGURE 3. SOFT START INTERVAL
SOFT-START
(1V/DIV.)
t
1
(2V/DIV.)
PGOOD
TIME (5ms/DIV.)
t
2
t
3
2
and t
1
2
. With sufficient
in Figure 3, the
VOLTAGE
OUTPUT
(1V/DIV.)
3
in Figure 3.
DS(ON)