ISL9440BIRZ-T Intersil, ISL9440BIRZ-T Datasheet - Page 17

• Manufacturer Part Number: ISL9440BIRZ-T
• Description: IC CTRLR PWM OUT-OF-PHASE 32-QFN
• Manufacturer: Intersil

Specifications of ISL9440BIRZ-T

• Pwm Type: Current Mode
• Number Of Outputs: 4
• Frequency - Max: 340kHz
• Duty Cycle: 93%
• Voltage - Supply: 4.5 V ~ 24 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Frequency-max: 340kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
General Description
The ISL9440B and ISL9440C integrate control circuits for
three synchronous buck converters and one linear controller.
The three synchronous bucks operate out-of-phase to
substantially reduce the input ripple and thus reduce the
input filter requirements. Each part has 3 control lines
(EN/SS1, EN/SS2 and EN/SS3), which provide independent
control and programmable soft-start for each of the
synchronous buck outputs.
The buck PWM controllers employ free-running frequency of
300kHz (ISL9440B) and 600kHz (ISL9440C). The current
mode control scheme with an input voltage feed-forward
ramp input to the PWM modulator provides an excellent
rejection of input voltage variations and simplifies loop
compensation design.
The linear controller can drive either a PNP bipolar junction
transistor or P-Channel MOSFET to provide ultra low-dropout
regulation with programmable voltages.
Internal 5V Linear Regulator (VCC_5V)
All ISL9440B and ISL9440C functions are internally powered
from an on-chip, low dropout 5V regulator. The maximum
regulator input voltage is 24V. Bypass the regulator’s output
(VCC_5V) with a 4.7µF capacitor to ground. The dropout
voltage for this LDO is typically 600mV, so when V
greater than 5.6V, VCC_5V is typically 5V. The ISL9440B
and ISL9440C also employ an undervoltage lockout circuit
that disables both regulators when VCC_5V falls below 3.7V.
The internal LDO can source over 60mA to supply the IC,
power the low-side gate drivers and charge the external boot
capacitor. When driving large FETs especially at 300kHz
frequency, little or no regulator current may be available for
external loads.
For example, a single large FET with 15nC total gate charge
requires 15nC x 300kHz = 4.5mA (15nC x 600kHz = 9mA).
Also, at higher input voltages with larger FETs, the power
dissipation across the internal 5V will increase. Excessive
dissipation across this regulator must be avoided to prevent
junction temperature rise. Larger FETs can be used with 5V
±10% input applications. The thermal overload protection
circuit will be triggered, if the VCC_5V output is short-circuit.
Connect VCC_5V to V
Enable Signals and Soft-Start Operation
The typical applications for the ISL9440B and ISL9440C are
using programmable analog soft-start. The soft-start time
can be set by the value of the soft-start capacitors connected
from the EN/SSx pins to the ground. The start-up in-rush
current can be alleviated by adjusting the soft starting time.
After the VCC_5V pin reaches the UVLO threshold, the
ISL9440B and ISL9440C soft-start circuitry becomes active.
The internal 1.55µA charge current begins charging up the
IN
for 5V ±10% input applications.
17
IN
ISL9440B, ISL9440C
is
soft-start capacitors connected from the EN/SSx pin to the
GND. The PWM output remains inactive until the voltage on
the corresponding EN/SSx pin reaches 1.3V. After that, the
reference voltage is clamped to the voltage on the EN/SSx
pin minus 1.3V. Then the output voltage ramps up with the
voltage on EN/SSx until the voltage reaches 2.1V. The
charging continues until the voltage on the EN/SSx reaches
3.5V.
Each PWM output can be disabled by pulling the
corresponding EN/SSx to the ground.
PGOOD will not toggle to high until soft-start is complete and
all the four outputs are up and in regulations.
Output Voltage Programming
The ISL9440B and ISL9440C use a precision internal
reference voltage to set the output voltage. Based on this
internal reference, the output voltage can thus be set from
0.8V up to a level determined by the input voltage, the
maximum duty cycle, and the conversion efficiency of the
circuit.
A resistive divider from the output to ground sets the output
voltage of either PWM channel. The center point of the
divider shall be connected to the FBx pin. The output voltage
value is determined by Equation 2.
Where R1 is the top resistor of the feedback divider network
and R2 is the resistor connected from FBx to ground.
Out-of-Phase Operation
To reduce input ripple current, Channel 1 and Channel 2
operate 180° out-of-phase, Channel 3 keeps 0° phase with
Channel 1. Channel 1 and Channel 2 typically output higher
load compared to Channel 3 because of their stronger drivers.
This reduces the input capacitor ripple current requirements,
reduces power supply-induced noise, and improves EMI. This
effectively helps to lower component cost, save board space
and reduce EMI.
Triple PWMs typically operate in-phase and turn on both upper
FETs at the same time. The input capacitor must then support
the instantaneous current requirements of the three switching
regulators simultaneously, resulting in increased ripple voltage
and current. The higher RMS ripple current lowers the
efficiency due to the power loss associated with the ESR of the
input capacitor. This typically requires more low-ESR capacitors
in parallel to minimize the input voltage ripple and ESR-related
losses, or to meet the required ripple current rating.
With synchronized out-of-phase operation, the high-side
MOSFETs turn on 180° out-of-phase. The instantaneous input
current peaks of both regulators no longer overlap, resulting in
reduced RMS ripple current and input voltage ripple. This
reduces the required input capacitor ripple current rating,
allowing fewer or less expensive capacitors, and reducing the
V
OUTx
=
0.8V
⎛
⎝
R1
--------------------- -
R2
+
R2
⎞
⎠
June 24, 2010
FN6799.3
(EQ. 2)