ISL6326CRZ-T Intersil, ISL6326CRZ-T Datasheet - Page 20

• Manufacturer Part Number: ISL6326CRZ-T
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6326CRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 25%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

t
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum t
During t
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R
second soft-start ramp time t
based on Equations 15 and 16:
For example, when VID is set to 1.5V and the R
100kΩ, the first soft-start ramp time t
second soft-start ramp time t
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t
typical value for t
Fault Monitoring and Protection
The ISL6326 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 9 outlines
the interaction between the fault monitors and the VR_RDY
signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period has completed and the output
voltage is within the regulated range. VR_RDY is pulled low
during shutdown and releases high after a successful
soft-start and a fixed delay t
t
t
d1
d2
d4
is a fixed delay with the typical value as 1.36ms. t
=
=
1.1xR
----------------------- - μs
(
------------------------------------------------ μs
6.25x25
V
d2
VID
and t
6.25x25
FIGURE 8. SOFT-START WAVEFORMS
SS
–
1.1
(
V
d4
)xR
OUT
d5
t
d1
)
, ISL6326 digitally controls the DAC
is 85µs.
SS
, 500mV/DIV
EN_VTT
VR_RDY
(
d3
)
t
SS
d2
d4
is about 86µs.
d5
500µs/DIV
d2
20
. VR_RDY will be pulled low
from SS pin to GND. The
will be 256µs.
and t
t
d3
d2
d4
t
d4
will be 704µs and the
can be calculated
t
d5
SS
d5
. The
is set at
(EQ. 15)
d3
(EQ. 16)
is
ISL6326
when an undervoltage or overvoltage condition is detected,
or the controller is disabled by a reset from EN_PWR,
EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6326
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during
the soft-start intervals t
1.275V. Once the controller detects valid VID input, the OVP
trip point will be changed to DAC + 175mV.
Two actions are taken by the ISL6326 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (>20ns). This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC + 75mV, PWM
signals enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both
upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6326 will again command the lower
MOSFETs to turn on. The ISL6326 will continue to protect
the load in this fashion as long as the overvoltage condition
occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6326 is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the
POR-falling threshold will reset the controller. Cycling the
VID codes will not reset the controller..
VDIFF
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
DAC
50%
VID + 0.175V
UV
+
-
AND CONTROL LOGIC
OV
SOFT-START, FAULT
d1
, t
d2
and t
d3
, the OVP threshold is
OC
+
-
VR_RDY
May 5, 2008
FN9262.1
85µA
I
AVG