ISL6326CRZ-T Intersil, ISL6326CRZ-T Datasheet - Page 19

• Manufacturer Part Number: ISL6326CRZ-T
• Description: IC CTRLR PWM 4PHASE BUCK 40-QFN
• Manufacturer: Intersil

Specifications of ISL6326CRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 25%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core voltage
regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R
used. The selection of R
voltage as detailed above in “Output Voltage Offset
Programming” on page 18. The selection of C
on the time duration for 1-bit VID change and the allowable
delay time.
Assuming the microprocessor controls the VID change at
1-bit every t
of R
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6326 is
released from shutdown mode.
C
1. The bias voltage applied at VCC must reach the internal
2. The ISL6326 features an enable input (EN_PWR) for
REF
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6326 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6326 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 6).
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6326 in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6326 becomes enabled. The schematic in Figure 7
demonstrates sequencing the ISL6326 with the ISL66xx
REF
R
REF
and C
VID
=
REF
REF
, the relationship between the time constant
T
VID
network and t
and C
REF
REF
19
is based on the desired offset
, as shown in Figure 6, can be
VID
is given by Equation 13:
REF
is based
(EQ. 13)
ISL6326
When all conditions are satisfied, ISL6326 begins the
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6326 reads the VID
code at VID input pins. If the VID code is valid, ISL6326 will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6326 will shutdown, and cycling VCC,
EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6326 based VR has 4 periods during soft-start as shown
in Figure 8. After VCC, EN_VTT and EN_PWR reach their
POR/enable thresholds, The controller will have fixed delay
period t
soft-start ramp until the output voltage reaches 1.1V V
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period t
ISL6326 reads the VID signals. If the VID code is valid,
ISL6326 will initiate the second soft-start ramp until the
voltage reaches the VID voltage minus offset voltage.
The soft-start time is the sum of the 4 periods, as shown in
Equation 14:
t
3. The voltage on EN_VTT must be higher than 0.875V to
SS
FIGURE 7. POWER SEQUENCING USING THRESHOLD-
family of Intersil MOSFET drivers, which require 12V
bias.
enable the controller. This pin is typically connected to the
output of VTT VR.
=
t
FAULT LOGIC
d1
SOFT-START
CIRCUIT
d1
POR
. After this delay period, the VR will begin first
+
AND
t
ISL6326 INTERNAL CIRCUIT
d2
SENSITIVE ENABLE (EN) FUNCTION
+
t
d3
+
t
COMPARATOR
d4
ENABLE
+
-
0.875V
+
d3
-
0.875V
. At the end of t
EXTERNAL CIRCUIT
VCC
EN_VTT
EN_PWR
10kΩ
910Ω
d3
+12V
period,
May 5, 2008
(EQ. 14)
FN9262.1
BOOT