ISL6308ACRZ-T Intersil, ISL6308ACRZ-T Datasheet - Page 25

• Manufacturer Part Number: ISL6308ACRZ-T
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6308ACRZ-T

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 275kHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 5.25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 275kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
For a three-phase design, use Figure 24 to determine the
input-capacitor RMS current requirement set by the duty
cycle, maximum sustained output current (I
of the peak-to-peak inductor current (I
bulk capacitor with a ripple current rating which will minimize
the total number of input capacitors required to support the
RMS current calculated. The voltage rating of the capacitors
should also be at least 1.25 times greater than the maximum
input voltage. Figures 25 and 26 provide the same input
RMS current information for two-phase and single-phase
designs respectively. Use the same approach for selecting
the bulk capacitor type and number.
FIGURE 24. NORMALIZED INPUT-CAPACITOR RMS
0.3
0.2
0.1
0
0
200
100
50
20
10
FIGURE 23. R
I
I
L,PP
L,PP
100k
CURRENT FOR 3-PHASE CONVERTER
= 0
= 0.25 I
0.2
SWITCHING FREQUENCY (Hz)
O
200k
FS
DUTY CYCLE (V
vs SWITCHING FREQUENCY
0.4
25
I
I
L,PP
L,PP
500k
0.6
= 0.5 I
= 0.75 I
IN/
L,PP
V
O
1M
)
) to I
O
O
O
), and the ratio
0.8
O
. Select a
2M
1.0
ISL6308A
Low ESL, high-frequency ceramic capacitors are needed in
addition to the input bulk capacitors to suppress leading and
falling edge voltage spikes. The spikes result from the high
current slew rate produced by the upper MOSFET turn on
and off. Place them as close as possible to each upper
MOSFET drain to minimize board parasitics and maximize
suppression.
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS
FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS
0.6
0.4
0.2
0.3
0.2
0.1
0
0
0
0
I
I
I
L,PP
L,PP
L,PP
I
I
I
CURRENT FOR SINGLE-PHASE CONVERTER
CURRENT FOR 2-PHASE CONVERTER
L,PP
L,PP
L,PP
= 0
= 0.5 I
= 0.75 I
0.2
0.2
= 0
= 0.5 I
= 0.75 I
O
O
DUTY CYCLE (V
DUTY CYCLE (V
O
O
0.4
0.4
0.6
0.6
IN
IN/
/V
V
O
O
)
)
0.8
0.8
September 9, 2008
FN6669.0
1.0
1.0