ISL6540AIRZ Intersil, ISL6540AIRZ Datasheet - Page 15

• Manufacturer Part Number: ISL6540AIRZ
• Description: IC CTRLR PWM BUCK 1PHASE 28-QFN
• Manufacturer: Intersil

Specifications of ISL6540AIRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 2MHz
• Duty Cycle: 100%
• Voltage - Supply: 2.97 V ~ 22 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Frequency-max: 2MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Internal Reference and System Accuracy
The internal reference is trimmed to 0.591V. The total DC
system accuracy of the system is within ±0.68% over
commercial temperature range, and ±1.00% over industrial
temperature range. System accuracy includes error amplifier
offset, OTA error, and bandgap error. Differential remote
sense offset error is not included. As a result, if the
differential remote sense is used, then an extra 1.9mV of
offset error enters the system. The use of REFIN may add
up to 2.2mV of additional offset error.
Differential Remote Sense Buffer
The differential remote sense buffer is essentially an
instrumentation amplifier with unity gain. The offset is
trimmed to 1.5mV for high system accuracy. As with any
instrumentation amplifier, typically 6µA are sourced from the
VSEN- pin. The output of the remote sense buffer is
connected directly to the internal OV/UV comparator. As a
result, a resistor divider should be placed on the input of the
buffer for proper regulation, as shown in Figure 6. The
VMON pin should be connected to the FB pin by a standard
feed-back network. A small capacitor, C
be added to filter out noise, typically C
corresponding time constant does not reduce the overall
phase margin of the design, typically this is 2x to 10x
switching frequency of the regulator.
As some applications will not use the differential remote
sense, the output of the remote sense buffer can be disabled
(high impedance) by pulling VSEN- within 1.8V of VCC. As
the VMON pin is connected internally to the OV/UV/PGOOD
comparator, an external resistor divider must then be
connected to VMON to provide correct voltage information
for the OV/UV comparator. An RC filter should be used if
VOUT (LOCAL)
GND (LOCAL)
FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION
15
1.8V
VCC
SEN
10Ω
SEN
10Ω
is chosen so the
(REMOTE)
VSENSE-
in Figure 6, can
VSEN-
R
C
OS
SEN
(REMOTE)
VSENSE+
ISL6540A
VSEN+
R
GAIN=1
FB
V
SS
VMON is to be connected directly to FB instead of to VOUT
through a separate resistor divider network. This filter
prevents noise injection from disturbing the OV/UV/PGOOD
comparators on VMON. VMON may also be connected to
the SS pin, which completely bypasses the OV/UV/PGOOD
functionality.
Application Guidelines
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET is carrying the output inductor current.
During the turnoff, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET. Any
inductance in the switched current path generates a large
voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide circuit traces minimize the magnitude of
voltage spikes.
There are two sets of critical components in a DC/DC
converter using a ISL6540A controller. The power
components are the most critical because they switch large
currents and have the potential to create large voltage
spikes, as well as induce noise into sensitive, high
impedance adjacent nodes. Next are small signal
VMON
Z
OV/UV
COMP
IN
ERROR AMP
FB
Z
FB
COMP
October 7, 2008
FN6288.5