LT3150CGN#PBF Linear Technology, LT3150CGN#PBF Datasheet - Page 7

• Manufacturer Part Number: LT3150CGN#PBF
• Description: IC CTRLR REG VLDO FET 16-SSOP
• Manufacturer: Linear Technology
• Type: Positive Adjustabler

Specifications of LT3150CGN#PBF

• Number Of Outputs: 1
• Voltage - Output: 2.5 ~ 18.4 V
• Current - Supply: 12mA
• Voltage - Input: 1.5 ~ 10 V, 10 ~ 20 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 16-SSOP
• Primary Input Voltage: 10V
• Dropout Voltage Vdo: 130mV
• No. Of Pins: 16
• Output Current: 10A
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 1 - Unlimited
• Output Voltage Adjustable Min, Vout: 1.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PI FU CTIO S
V
control circuitry and provides sufficient gate drive compli-
ance for the external N-channel MOSFET. The maximum
operating V
set by V
(worst-case V
GND (Pin 6): Analog Ground. This pin is also the negative
sense terminal for the internal 1.21V reference. Connect the
LDO regulator external feedback divider network and fre-
quency compensation components that terminate to GND
directly to this pin for best regulation and performance. Also,
tie this pin directly to SWGND (Pin 2) and GND (Pin 15).
NC (Pins 7, 10): No Connect.
FB2 (Pin 8): This is the inverting input of the error amplifier
for the linear regulator. The noninverting input is tied to the
internal 1.21V reference. Input bias current for this pin is
typically 0.6 A flowing out of the pin. Tie this pin to a
resistor divider network to set output voltage. Tie the top
of the external resistor divider directly to the output load
for best regulation performance.
COMP (Pin 9): This is the high impedance gain node of the
error amplifier and is used for external frequency compen-
sation. The transconductance of the error amplifier is 15
millimhos and open-loop voltage gain is typically 84dB.
Frequency compensation is generally performed with a
series RC + C network to ground.
GATE (Pin 11): This is the output of the error amplifier
that drives N-channel MOSFETs with up to 5000pF of
“effective” gate capacitance. The typical open-loop out-
put impedance is 2 . When using low input capacitance
MOSFETs (< 1500pF), a small gate resistor of 2 to 10
dampens high frequency ringing created by an LC reso-
nance due to the MOSFET gate’s lead inductance and
input capacitance. The GATE pin delivers up to 50mA for
a few hundred nanoseconds when slewing the gate of the
N-channel MOSFET in response to output load current
transients.
IN2
U
(Pin 5): This is the input supply for the linear regulator
OUT
U
IN2
+ (V
IN2
is 20V and the minimum operating V
GS
to GATE output swing).
U
of the MOSFET at max I
OUT
) + 1.6V
IN2
is
I
current limit amplifier. A small sense resistor is connected
in series with the drain of the external MOSFET and is
connected between the I
threshold voltage in conjunction with the sense resistor
value sets the current limit level. The current sense resis-
tor can be a low value shunt or can be made from a piece
of PC board trace. If the current limit amplifier is not used,
tie the I
is to ground the I
limit amplifier and additional internal circuitry activates
the timer circuit on the SHDN2 pin if the GATE pin swings
to the V
No R
I
current limit amplifier. Tie this pin directly to the main
input voltage from which the output voltage is regulated.
SHDN1 (Pin 14): Boost Regulator Shutdown Pin. Tie to 1V
or more to enable device. Ground to shut down. This pin
must not float for proper operation. Connect SHDN1
externally as it does not incorporate an internal pull-up or
pull-down.
GND (Pin 15): Boost Converter Analog Ground. This pin
is also the negative sense terminal for the FB1 1.23V
reference. Connect the external feedback divider net-
work, which sets the V
to GND, directly to this pin for best regulation and
performance. Also, tie this pin directly to SWGND (Pin 2)
and GND (Pin 6).
FB1 (Pin 16): Boost Regulator Feedback Pin. Reference
voltage is 1.23V. Connect resistive divider tap here.
Minimize trace area at FB1. Set V
V
No R
NEG
POS
OUT
SENSE
(Pin 12): This is the negative sense terminal of the
SENSE
(Pin 13): This is the positive sense terminal of the
= 1.23V(1 + R1/R2).
NEG
is a trademark of Linear Technology Corporation.
IN
TM
pin to I
rail. This option provides the user with a
current limit function.
NEG
POS
pin. This action disables the current
to defeat current limit. An alternative
IN2
supply voltage and terminates
POS
and I
OUT
NEG
= V
IN2
pins. A 50mV
according to
LT3150
7
3150f