STTS424E02BDN3F STMicroelectronics, STTS424E02BDN3F Datasheet - Page 20

• Manufacturer Part Number: STTS424E02BDN3F
• Description: IC TEMP SENSOR 2KB EEPRM 8-TDFN
• Manufacturer: STMicroelectronics

Specifications of STTS424E02BDN3F

• Function: Temp Monitoring System (Sensor)
• Topology: ADC (Sigma Delta), Register Bank
• Sensor Type: Internal
• Sensing Temperature: -40°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN
• Temperature Threshold: + 150 C
• Full Temp Accuracy: +/- 1 C
• Digital Output - Bus Interface: 2-Wire, I2C
• Digital Output - Number Of Bits: 10 bit
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Current: 100 uA
• For Use With: 497-8843 - EVAL DAUGHTER STTS424E02 8-TDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8284-2

Temperature sensor registers
Table 9.
20/50
Bit
0
1
2
3
4
5
6
7
8
Event mode
– 0 = Comparator output mode (this is the default).
– 1 = Interrupt mode; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
Event polarity
The event polarity bit controls the active state of the EVENT pin. The EVENT pin is driven to this state
when it is asserted.
– 0 = Active-low (this is the default). Requires a pull-up resistor to set the inactive state of the open-
– 1 = Active-high. The active state of the pin is then logical “1”.
Critical event only
– 0 = Event output on alarm or critical temperature event (this is the default).
– 1 = Event only if the temperature is above the value in the critical temperature register; when the alarm
Event output control
– 0 = Event output disabled (this is the default).
– 1 = Event output enabled; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
Event status (read-only)
– 0 = Event output condition is not being asserted by this device.
– 1 = Event output condition is being asserted by this device via the alarm window or critical trip event.
Clear event (write-only)
– 0 = No effect.
– 1 = Clears the active event in interrupt mode.
Alarm window lock bit
– 0 = Alarm trips are not locked and can be altered (this is the default).
– 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
Critical trip lock bit
– 0 = Critical trip is not locked and can be altered (this is the default).
– 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
Shutdown mode
– 0 = TS is enabled (this is the default).
– 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No
drain output. The power to the pull-up resistor should not be greater than V
state is logical “0”.
window lock bit is set, this bit cannot be altered until it is unlocked.
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
event conditions will be asserted; when either of the lock bits is set, this bit cannot be altered until it is
unlocked. However, it can be cleared at any time.
Configuration register bit definitions
(1)
(3)
(2)
Doc ID 13448 Rev 8
Definition
DD
+ 0.2 V. Active
STTS424E02