ADT7518ARQ-REEL Analog Devices Inc, ADT7518ARQ-REEL Datasheet - Page 9

• Manufacturer Part Number: ADT7518ARQ-REEL
• Description: IC SENSOR TEMP W/ADC/DAC 16QSOP
• Manufacturer: Analog Devices Inc

Specifications of ADT7518ARQ-REEL

• Rohs Status: RoHS non-compliant
• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 120°C, External Sensor
• Output Type: I²C™, MICROWIRE™, QSPI™, SPI™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 120°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
V
V
V
CS
GND
V
D+/AIN1
D–/AIN2
LDAC/AIN3
INT/INT
DOUT/ADD
SDA/DIN
SCL/SCLK
AIN4
V
V
OUT
OUT
REF
DD
OUT
OUT
-IN
-B
-A
-D
-C
Description
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Reference Input Pin for All Four DACs. This input is buffered and has an input range from 1 V to V
SPI Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes low, it enables
the input register, and data is transferred in on the rising edges and out on the falling edges of the subsequent serial
clocks. It is recommended that this pin be tied high to V
Ground Reference Point for All Circuitry on the Part. Analog and digital ground.
Positive Supply Voltage, 2.7 V to 5.5 V. The supply should be decoupled to ground.
D+. Positive Connection to External Temperature Sensor. AIN1. Analog Input. Single-ended analog input channel.
Input range is 0 V to 2.25 V or 0 V to V
D–. Negative Connection to External Temperature Sensor.
AIN2. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
LDAC. Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. A
falling edge on this pin forces any or all DAC registers to be updated if the input registers have new data. A minimum
pulse width of 20 ns must be applied to the LDAC pin to ensure proper loading of a DAC register. This allows simul-
taneous update of all DAC outputs. Bit C3 of the Control Configuration 3 register enables the LDAC pin. Default is
with the LDAC pin controlling the loading of the DAC registers.
AIN3. Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
Over Limit Interrupt. The output polarity of this pin can be set to give an active low or active high interrupt when
temperature,V
SPI Serial Data Output. Logic output. Data is clocked out of any register at this pin. Data is clocked out on the falling
edge of SCLK. Open-drain output—needs a pull-up resistor.
ADD. I
gives the address 1001 010; and setting it high gives the address 1001 011. The I
not latched by the device until after this address has been sent twice. On the eighth SCL cycle of the second valid
communication, the serial bus address is latched in. Any subsequent changes on this pin will have no effect on the
I
SDA. I
provided on this pin. Open-drain configuration—needs a pull-up resistor.
DIN. SPI Serial Data Input. Serial data to be loaded into the part’s registers is provided on this pin. Data is clocked into
a register on the rising edge of SCLK. Open-drain configuration—needs a pull-up resistor.
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock data out of any register of
the ADT7518 and also to clock data into any register that can be written to. Open-drain configuration—needs a pull-
up resistor.
Analog Input. Single-ended analog input channel. Input range is 0 V to 2.25 V or 0 V to V
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
2
C serial bus address.
2
2
C Serial Data Input/Output. I
C Serial Bus Address Selection Pin. Logic input. A low on this pin gives the address 1001 000; leaving it floating
DD
, or AIN limits are exceeded. The default is active low. Open-drain output—needs a pull-up resistor.
D+/AIN1
D–/AIN2
V
V
V
REF
OUT
OUT
GND
V
CS
-IN
DD
-B
-A
Figure 7. Pin Configuration QSOP
2
C serial data to be loaded into the part’s registers and read from these registers is
1
2
3
4
5
6
7
8
DD
(Not to Scale)
.
Rev. A | Page 9 of 40
ADT7518
TOP VIEW
16
15
14
13
12
11
10
9
V
V
AIN4
SCL/SCLK
SDA/DIN
DOUT/ADD
INT/INT
LDAC/AIN3
OUT
OUT
DD
-C
-D
when operating the serial interface in I
2
C address set up by the ADD pin is
DD
.
DD
DD
.
.
DD
2
C mode.
.
ADT7518