MAX6604AATA+T Maxim Integrated Products, MAX6604AATA+T Datasheet - Page 5

• Manufacturer Part Number: MAX6604AATA+T
• Description: IC TEMP SENSOR DDR PREC 8-TDFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX6604AATA+T

• Function: Temp Monitoring System (Sensor)
• Sensor Type: Internal
• Sensing Temperature: -20°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-TDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Topology: -

The MAX6604 high-precision temperature sensor con-
tinuously monitors temperature and updates the
temperature data eight times per second. The device
functions as a slave on the SMBus/I
face. The master can read the temperature data at any
time through the digital interface. The MAX6604 also
features an open-drain, event-output indicator for tem-
perature-threshold monitoring.
The MAX6604 is readable and programmable through
the SMBus/I
tions as a slave on the interface. Figure 1 shows the
general timing diagram of the clock (SCL) and the data
(SDA) signals for the SMBus/I
The SDA and SCL bus lines are at logic-high when the
bus is not in use. Pullup resistors from the bus lines to
the supply are required when push-pull circuitry is not
driving the lines. The data on the SDA line can change
only when the SCL line is low. Start and stop conditions
occur when SDA changes state while the SCL line is
high (Figure 1). Data on SDA must be stable for the
duration of the setup time (t
high. Data on SDA is sampled when SCL toggles high
with data on SDA is stable for the duration of the hold
time (t
ted in an 8-bit byte. A total of nine clock cycles are
required to transfer a byte to the MAX6604. Since the
MAX6604 employs 16-bit registers, data is transmitted
or received in two 8-bit bytes (16 bits). The device
acknowledges the successful receipt for each byte by
pulling the SDA line low (issuing an ACK) during the
ninth clock cycle of each byte transfer.
Figure 1. SDA and SCL Timing Diagram
SDA
SCL
START CONDITION
HD:DAT
2
C-compatible interface. The device func-
). Note that a segment of data is transmit-
t
HD:STA
_______________________________________________________________________________________
t
R
Detailed Description
t
SU:DAT
SU:DAT
2
C-compatible interface.
t
F
Precision Temperature Monitor for
2
Serial Interface
) before SCL goes
C-compatible inter-
t
HD:DAT
SMBus/I
2
C
t
LOW
t
REPEATED START CONDITION
SU:STA
From a software perspective, the MAX6604 appears as a
set of 16-bit registers that contain temperature data,
alarm threshold values, and control bits. A standard
SMBus/I
perature data and writes control bits and alarm threshold
data. Each device responds to its own SMBus/I
address, which is selected using A0, A1, and A2. See
the Device Addressing section for details.
The MAX6604 employs standard I
using 16-bit registers: write word and read word. Write
a word of data (16 bits) by first sending MAX6604’s I
address (0011-A2-A1-A0-0), then sending the 8-bit
command byte, followed by the first 8-bit data byte.
Note that the slave issues an acknowledge after each
byte is written. After the first 8-bit data byte is written,
the MAX6604 also returns an acknowledge. However,
the master does not generate a stop condition after the
first byte has been written. The master continues to
write the second byte of data with the slave acknowl-
edging. After the second byte has been written, the
master then generates a stop condition. See Figure 2.
To read a word of data, the master generates a new
start condition and sends MAX6604’s I
the R/W bit low (0011-A2-A1-A0-0), then sends the 8-bit
command byte. Again, the MAX6604 issues an ACK for
each byte received. The master again sends the device
address with the R/W bit high (0011-A2-A1-A0-1), fol-
lowing an acknowledge. Next, the master reads the
contents of the selected register, beginning with the
most significant bit, and acknowledges if the most sig-
nificant data byte is successfully received. Finally, the
master reads the least significant data byte and issues
a NACK, followed by a stop condition to terminate the
read cycle.
DDR Memory Modules
2
t
C-compatible, 2-wire serial interface reads tem-
HD:STA
t
SU:STO
2
C/SMBus protocols
STOP CONDITION
2
C address with
t
BUF
2
C slave
2
C
5