LM96000CIMT/NOPB National Semiconductor, LM96000CIMT/NOPB Datasheet - Page 20

• Manufacturer Part Number: LM96000CIMT/NOPB
• Description: IC HDWR MON W/FAN CTRL 24-TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM96000CIMT/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Control, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Ic Output Type: Digital
• Sensing Accuracy Range: ± 2.5°C
• Temperature Sensing Range: 0°C To +85°C
• Supply Current: 530µA
• Supply Voltage Range: 3V To 3.6V
• Resolution (bits): 8bit
• Sensor Case Style: TSSOP
• No. Of Pins: 24
• Rohs Compliant: Yes
• Accuracy %: 3°C
• For Use With: LM96000EVAL - BOARD EVALUATION LM96000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM96000CIMT; *LM96000CIMT/NOPB; LM96000CIMT

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Register
Address
54h
55h
56h
57h
58h
59h
5Ah
5Bh
4.13 Registers 54-5Bh: Fan Tachometer Low Limit
The Fan Tachometer Low Limit registers indicate the tachometer reading under which the corresponding bit will be set in the
Interrupt Status Register 2 register. In Auto Fan Control mode, the fan can run at low speeds, so care should be taken in software
to ensure that the limit is high enough not to cause sporadic alerts. The fan tachometer will not cause a bit to be set in Interrupt
Status Register 2 if the current value in Current PWM Duty registers is 00h or if the fan 1 disabled via the Fan Configuration Register.
Interrupts will never be generated for a fan if its minimum is set to FF FFh.
Given the insignificance of Bit 0 and Bit 1, these bits could be programmed to remember which fan is which, as follows.
Setting the Ready/Lock/Start/Override register Lock bit has no effect these registers.
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register
Name
Tach1 Minimum LSB
Tach1 Minimum MSB
Tach2 Minimum LSB
Tach2 Minimum MSB
Tach3 Minimum LSB
Tach3 Minimum MSB
Tach4 Minimum LSB
Tach4 Minimum MSB
Fan
CPU
Memory
Chassis Front
Chassis Rear
Bit 7
(MSB)
7
15
7
15
7
15
7
15
Bit 6
6
14
6
14
6
14
6
14
20
Bit 5
5
13
5
13
5
13
5
13
Bit 1
0
0
1
1
Bit 4
4
12
4
12
4
12
4
12
Bit 0
0
1
0
1
Bit 3
3
11
3
11
3
11
3
11
Bit 2
2
10
2
10
2
10
2
10
Bit 1
1
9
1
9
1
9
1
9
Bit 0
(LSB)
0
8
0
8
0
8
0
8
Default
Value
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh