LM63CIMA/NOPB National Semiconductor, LM63CIMA/NOPB Datasheet - Page 6

• Manufacturer Part Number: LM63CIMA/NOPB
• Description: IC TEMP SENSR REMOTE DIODE 8SOIC
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM63CIMA/NOPB

• Function: Fan Control, Temp Monitor
• Topology: ADC (Sigma Delta), Comparator, Fan Speed Control, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Ic Output Type: Digital
• Sensing Accuracy Range: ± 1°C
• Supply Current: 1.3mA
• Supply Voltage Range: 3V To 3.6V
• Resolution (bits): 11bit
• Sensor Case Style: SOIC
• No. Of Pins: 8
• Termination Type: SMD
• Rohs Compliant: Yes
• Filter Terminals: SMD
• Accuracy %: 1°C
• For Use With: LM63EVAL - BOARD EVALUATION LM63
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM63CIMA; LM63CIMA

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f
t
t
t
t
t
t
t
t
t
t
t
t
SMB
LOW
HIGH
R
F
OF
TIMEOUT
SU:DAT
HD:DAT
HD:STA
SU:STO
SU:STA
BUF
Symbol
SMBus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for V
pF. Boldface limits apply for T
characteristics of the LM63 fully meet or exceed the published specifications of the SMBus version 2.0. The following parameters
are the timing relationships between SMBCLK and SMBDAT signals related to the LM63. They adhere to, but are not necessarily
the same as the SMBus bus specifications.
SMBus Clock Frequency
SMBus Clock Low Time
SMBus Clock High Time
SMBus Rise Time
SMBus Fall Time
Output Fall Time
SMBData and SMBCLK Time Low for Reset of
Serial Interface See
Data In Setup Time to SMBCLK High
Data Out Hold Time after SMBCLK Low
Hold Time after (Repeated) Start Condition. After
this period the first clock is generated.
Stop Condition SMBCLK High to SMBDAT Low
(Stop Condition Setup)
SMBus Repeated Start-Condition Setup Time,
SMBCLK High to SMBDAT Low
SMBus Free Time between Stop and Start
Conditions
Parameter
(Note
A
SMBus Timing Diagram for SMBCLK and SMBDAT Signals
= T
13)
J
; T
MIN
≤
T
A
≤
T
MAX
DD
; all other limits T
= +3.0 VDC to +3.6 VDC, C
From V
From V
(Note
(Note
C
L
= 400 pF, I
6
11)
12)
IN(0) max
IN(1) min
A
O
to V
to V
= T
= 3 mA
Conditions
IN(1) min
J
IN(0) max
= +25°C, unless otherwise noted. The switching
L
(load capacitance) on output lines = 80
(Note
Limits
100
250
250
300
930
100
4.7
4.0
0.3
4.0
4.7
4.7
10
50
25
35
1
8)
20057004
kHz (max)
kHz (min)
ms (max)
µs (max)
µs (max)
µs (max)
ns (max)
ms (min)
ns (max)
µs (min)
µs (min)
ns (min)
ns (min)
µs (min)
ns (min)
µs (min)
µs (min)
(Limit)
Units