ADT7470ARQZ Analog Devices Inc, ADT7470ARQZ Datasheet - Page 12

• Manufacturer Part Number: ADT7470ARQZ
• Description: IC SENSOR TEMP FAN CTRLR 16QSOP
• Manufacturer: Analog Devices Inc

Specifications of ADT7470ARQZ

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Control, Register Bank
• Sensor Type: External
• Sensing Temperature: External Sensor
• Output Type: I²C™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Ic Output Type: Digital
• Sensing Accuracy Range: ± 12%
• Supply Current: 500µA
• Supply Voltage Range: 3V To 5.5V
• Sensor Case Style: QSOP
• No. Of Pins: 16
• Msl: MSL 3 - 168 Hours
• Termination Type: SMD
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Accuracy %: 12%
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADT7470EBZ - BOARD EVALUATION FOR ADT7470
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADT7470
READ OPERATIONS
The ADT7470 uses the following SMBus read protocols.
Receive Byte
This is useful when repeatedly reading a single register.
The register address must be set up previously. In this
operation, the master device receives a single byte from
a slave device, as follows:
1.
2.
3.
4.
5.
6.
In the ADT7470, the receive byte protocol is used to read a
single byte of data from a register whose address was previously
set by a send byte or write byte operation.
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices,
which allows an interrupting device to identify itself to the host
when multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt output
or can be used as an SMBALERT . One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
occurs:
1.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the read bit (high).
The addressed slave device asserts ACK on SDA.
The master receives a data byte.
The master asserts NO ACK on SDA.
The master asserts a stop condition on SDA
and the transaction ends.
SMBALERT is pulled low.
1
S
Figure 12. Single-Byte Write from a Register
ADDRESS
SLAVE
2
R
A
3
DATA
4
5
A
P
6
Rev. C | Page 12 of 40
2.
3.
4.
5.
SMBus TIMEOUT
The ADT7470 includes an SMBus timeout feature. If there is no
SMBus activity for more than 31 ms, the ADT7470 assumes that
the bus is locked and releases the bus. This prevents the device
from locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
Table 6. Configuration Register 1—Register 0x40
Bit Address and Value
Bit 3 TODIS = 0
Bit 3 TODIS = 1
Although the ADT7470 supports packet error checking (PEC),
its use is optional. It is triggered by supplying the extra clock
for the PEC byte. The PEC byte is calculated using CRC-8.
The frame check sequence (FCS) conforms to CRC-8 by the
following polynomial:
Consult the SMBus 1.1 Specification for more information by
searching online.
The master initiates a read operation and sends the alert
response address (ARA = 000 1100). This is a general call
address that must not be used as a specific device address.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known, and it
can be interrogated in the usual way.
If more than one device’s SMBALERT output is low,
the one with the lowest device address has priority,
in accordance with normal SMBus arbitration.
Once the ADT7470 responds to the alert response
address, the master must read the status registers,
and the SMBALERT is cleared only if the error condition
is gone.
C(x) = x
8
+ x
2
+ x
1
+ 1
Description
SMBus timeout enabled (default).
SMBus timeout disabled.