L6610N STMicroelectronics, L6610N Datasheet - Page 21

• Manufacturer Part Number: L6610N
• Description: IC CTRLR HOUSEKEEPING BCD 24-DIP
• Manufacturer: STMicroelectronics

Specifications of L6610N

• Applications: Programmable Housekeeping Controller
• Voltage - Supply: 4.2 V ~ 7 V
• Current - Supply: 5mA
• Operating Temperature: 0°C ~ 105°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

4
The IC provides on-board undervoltage and overvoltage protection for 3V3, ±5V, ±12V Main input pins and
Dmon auxiliary input pin. Overcurrent protection is available for 12V and 5V or 3.3V, digitally selectable. The
internal fault logic is illustrated in figure 21.
Figure 21. Simplified Fault logic
– Main inputs overvoltage: whenever one of main outputs (3.3V, ±5V, ±12V) is detected as going over-
– Main inputs undervoltage: when an undervoltage on main outputs is detected, MFAULT is latched
– Dmon input overvoltage: whenever the Dmon input pin is detected as going overvoltage, both
Main_OV
+/-12V_Main_UV
+3V3 +/-5V_Main_UV
Main_OC
ACsense
Dmon_OV
Dmon_UV
Vdd_OV
Vdd_UVL
Restart Mode
PS-ON
voltage, MFAULT is latched high (which stops the Main PWM) and PW-OK goes low. Cycling the PS-
ON switch or reducing Vdd below its undervoltage threshold releases the latch. A delay of 6µs is imple-
mented before MFAULT latching.
The OV protection for the 12V and 5V outputs can be disabled (see "On board trimming and mode op-
erating" section).
high (the Main PWM stops) and PW-OK goes low. The latches are released, by default, cycling the PS-
ON switch or reducing Vdd below its undervoltage threshold (latching mode); optionally, an attempt is
made to restart the supply after of 1 second (bounce mode). The choice depends on the selected mode
(see "On board trimming and mode operating" section).
Debounce logic is implemented for 3.3V and 5V so that an undervoltage condition on these signals has
to last 450µs to be recognized as valid while 6µs debounce logic is implemented for 12V and -12V input
signal. When all main undervoltages are over and ACsns is OK (see the relevant section), PW_OK goes
high after a delay of 250ms.
MFAULT and DFAULT are latched high. The latch is released by reducing Vdd below its undervoltage
threshold. Debounce logic is implemented so that MFAULT and DFAULT signals are latched only if the
overvoltage condition lasts more than 6µs.
To protect the load against overvoltage, typical solutions make use of a power crowbar (SCR) driven by
UNDERVOLTAGE, OVERVOLTAGE, OVERCURRENT DETECTION AND RELEVANT TIMINGS
Vdd
Vref
+
Reset
Debounce 75ms
Debounce 500 s
In
Clock
Debounce 6 s
In
Clock
In
Clock
Reset
Out
Reset
Out
Reset
Debounce 500 s
Reset
Out
In
ON
Clock
Reset
Reset
Out
Reset
S
R
Vdd
Latch
Vdd
Q
Debounce 6 s
In
In
In
UVB 64ms
Clock
Clock
Clock
Delay 1s
Debounce 6 s
In
In
Clock
Clock
UVB 64ms
Reset
Reset
Reset
Out
Out
Out
Reset
Reset
Reset
Out
Out
Reset
Reset
Reset
D_UVB
Delay 2.5ms
In
Clock
Reset
Out
Reset
Vdd
Delay 250ms
In
Clock
S
R
Latch
Reset
Reset
Q
Reset
Out
S
R
S
R
Latch
Latch
Q
Q
OCP_BOUNCE
Vdd
Vdd
Mfault
PW-OK
L6610
Dfault
Cout
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