ISL8724IRZ Intersil, ISL8724IRZ Datasheet - Page 6

• Manufacturer Part Number: ISL8724IRZ
• Description: IC POWER SUPPLY SEQUENCER 24QFN
• Manufacturer: Intersil

Specifications of ISL8724IRZ

• Applications: Power Supply Sequencer
• Voltage - Supply: 2.5 V ~ 5 V
• Current - Supply: 270µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -

that are on a common connection thus unconditionally
shutting down all outputs across multiple sequencers. As
an input, if it is pulled low all GATEs will be unconditionally
shut off and RESET pulled low (see Figure 18). This pin
can also be used as a ‘no wait’ enabling input if all inputs
(ENABLE and UVLO) are satisfied; it does not wait through
the ~10ms enable delay to initiate the DLY_ON capacitor
charging when released to go high. This feature can be
used where 4 voltages can be monitored in addition to a
on-off switch position or, in the case of the ISL8724, a
present pin pull-down.
Restart of the turn on sequence is automatic once all
requirements are met. This allows for no interaction
between the sequencer and a controller IC if so desired.
If no capacitors are connected between DLY_ON or
DLY_OFF pins and ground then all such related GATEs
start to turn on immediately after the 10ms (t
ENABLE stabilization time out has expired and the GATEs
start to immediately turn off when ENABLE is deasserted.
Table 1 illustrates the nominal time delay from the start of
charging to the 1.27V reference for various capacitor
values on the DLY_X pins. This table does not include the
10ms of enable lock out delay during a start-up sequence
but represents the time from the end of the enable lock out
l
ENABLE (ISL8724)
ENABLE (ISL8723)
DLYON_B
DLYON_D
DLYON_A
DLYON_C
UVLO_A
UVLO_B
UVLO_C
UVLO_D
GATE_B
GATE_D
GATE_C
GATE_A
SYSRST
RESET
FIGURE 3. ISL8723, ISL8724 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM
6
V
UVLOVth
V
V
UVLOVth
V
UVLOVth
UVLOdel
UVLOVth
ISL8723, ISL8724
)
t
UVLOdel
V
EN
DLY_Vth
delay to the start of GATE transition. There is no enable
lock out delay for a sequence off, so this table illustrates
the delay to GATE transition from a disable signal.
Figure 3 illustrates the turn-on and Figure 4 the nominal turnoff
timing diagrams of the ISL8723 and ISL8724 product.
Note the delay and flexible sequencing possibilities. Multiple
series, parallel or adjustable capacitors can be used to easily
fine tune timing between that offered by standard value
capacitors.
DLY_Vth
NOTE: Nom. T
DLY_Vth
DLY_Vth
NOMINAL DELAY TO SEQUENCING THRESHOLD
CAPACITANCE
DLY PIN
1000pF
0.01
100pF
0.1
V
Open
1
QPUMP
DEL_SEQ
µ
µ
F
µ
F
F
t
RSTdel
-1V
= dly_cap (µF)x1.35MΩ
TABLE 1.
<tFIL
V
V
V
V
QPUMP
QPUMP
QPUMP
QPUMP
0.135
TIME
1350
(ms)
0.02
1.35
13.5
135
April 22, 2009
FN6413.1