ISL8724IRZ Intersil, ISL8724IRZ Datasheet
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ISL8724IRZ
Specifications of ISL8724IRZ
Related parts for ISL8724IRZ
ISL8724IRZ Summary of contents
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... RANGE (Note) MARKING (°C) ISL8723IRZ* 87 23IRZ - 4x4 QFN L24.4x4 ISL8724IRZ* 87 24IRZ - 4x4 QFN L24.4x4 ISL8723EVAL1 Evaluation Platform *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ ...
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AIN BIN CIN DIN V DD UVLO_A ENABLE UVLO_B SYSRST UVLO_C RESET UVLO_D GROUND FIGURE 1. TYPICAL ISL8723 APPLICATION USAGE Pin Descriptions PIN PIN # NAME FUNCTION 23 VDD Chip Bias 10, 19 GND Bias Return 1 ENABLE/ Input to ...
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Pin Descriptions (Continued) PIN PIN # NAME FUNCTION 18 DLY_OFF_A Gate Off Delay Timer Output 13 DLY_OFF_B 3 DLY_OFF_C 4 DLY_OFF_D 2 GATE_A FET Gate Drive Output 5 GATE_B 6 GATE_C 7 GATE_D 22 SYSRST System Reset I ...
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... Ld 4x4 QFN Package . . . . . . . . . . . DD +0.3V DD Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C +0.3V Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C DD Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = T = -40°C to +85°C, Unless Otherwise Specified. Parameters with MIN and/or MAX A J SYMBOL TEST CONDITIONS +25° ...
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Electrical Specifications V = 3.3V to +5V limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER SYSRST Low Output Voltage SYSRST Output Capacitance SYSRST Low to ...
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As an input pulled low all GATEs will be unconditionally shut off and RESET pulled low (see Figure 18). This pin can ...
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UVLO_X>VUVLOVth ENABLE(ISL8723) ENABLE (ISL8724) DLYOFF_A DLYOFF_B DLYOFF_C DLYOFF_D GATE_C GATE_D GATE_A GATE_B RESET SYSRST FIGURE 4. ISL8723, ISL8724 TURN-OFF TIMING DIAGRAM Typical Performance Curves 0.30 0.25 0. 3.3V 0.15 0.10 0.05 0.00 -40 - ...
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Typical Performance Curves 1.29 DLY_OFF Vth 1.28 1.27 1.26 DLY_ON Vth 1.25 1.24 1.23 -40 - TEMPERATURE (°C) FIGURE 9. BIAS POWER ON RESET 10.3 10.2 10.1 10.0 9.9 I_GATE_OFF 9.8 9.7 9.6 9.5 9.4 -40 -20 ...
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Typical Performance Waveforms ENABLE SYSRST I/O = 5V/DIV 5VOUT 3.3VOUT 1.5VOUT VOUT = 2V/DIV FIGURE 13. ISL8723 SEQUENCED TURN-ON EN 5V/DIV t delENLO DLY_ON 0.5V/DIV FIGURE 15. ISL8723 3.3V TURN-ON FIGURE 17. SYSRST AND RESET vs VDD (EN = VDD, ...
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Typical Performance Waveforms FIGURE 19. 4 UVLOs VALID, ENABLE HIGH TO SYSRST HIGH 10 ISL8723, ISL8724 (Continued) SYSRST SYSRST RESET ENABLE ENABLE FIGURE 20. ENABLE LOW TO RESET AND SYSRST LOW UVLO RESET SYSRST FIGURE 21. UVLO INVALID TO RESET ...
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7.681k 4.99k 6.98k 8.45k R12 R5 R3 R11 4.99k 1.47k 2.26k 3.01k 1 22 SYSRST 9, ISL8723, ISL8724 + 1µ ...
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... The sequencing is straight forward across multiple sequencers as all DLY_ON capacitors will simultaneously 12 ISL8723, ISL8724 COMPONENT DESCRIPTION Intersil, ISL8723IR 4 Supply Sequencer FDS6990S or equivalent, Dual N-Channel MOSFET 8.45kΩ 1%, 0402 1.47kΩ 1%, 0402 7.68kΩ 1%, 0402 2.26kΩ 1%, 0402 6.98kΩ ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L24.4x4 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 10/06 4.00 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 14 ISL8723, ...