ISL97651ARTZ-TK Intersil, ISL97651ARTZ-TK Datasheet
ISL97651ARTZ-TK
Specifications of ISL97651ARTZ-TK
Related parts for ISL97651ARTZ-TK
ISL97651ARTZ-TK Summary of contents
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... Ordering Information PART NUMBER 27 AGND (Notes PGND1 ISL97651ARTZ-T 25 PGND2 ISL97651ARTZ-TK ISL976 51ARTZ 36 Ld 6x6 TQFN L36.6x6 24 VINL NOTES: 1. Please refer to TB347 for details on reel specifications. 23 NOUT 2. These Intersil Pb-free plastic packaged products employ special 22 PGND3 Pb-free material sets, molding compounds/die attach materials, ...
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... Maximum Junction Temperature (Plastic Package +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Power Dissipation ≤ +25° .3. +70° .1. +85° .1. +100° .0.8W A Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = V = 15V 25V, V BOOST SUP ON OFF CONDITIONS Slice ON Enabled, No switching IN Disabled Enabled, No switching Disabled ...
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Electrical Specifications with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER DESCRIPTION EFF Peak Efficiency BOOST r Switch ON-Resistance ...
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Electrical Specifications with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER DESCRIPTION POSITIVE (V ) CHARGE PUMP ON V ...
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Electrical Specifications with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER DESCRIPTION FAULT DETECTION THRESHOLDS T_off Thermal Shut-Down (latched ...
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Typical Performance Curves L1 = 10µ 40µF, CM1 = 4.7nF, RM1 OUT CH1 = A (200mV/DIV), CH2 = I VDD AVDD 1ms/DIV FIGURE 3. A TRANSIENT RESPONSE VDD 0 5V -0.1 -0.2 -0.3 ...
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Typical Performance Curves CH1 = COM(10V/DIV), CH2 = CTL(2V/DIV) 4ms/DIV FIGURE 9. V -SLICE CIRCUIT OPERATION ON 7 ISL97651 (Continued) CH1 = CH2 = V , CH3 = V CH4 = V DLY REF LOGIC, ...
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Pin Descriptions PIN NUMBER PIN NAME 1 VIN1 2 LX1 3 LX2 LXL 6 VSUP 7 FBL 8 CM2 9 CTL 10, 18, 28 DRN 12 COM 13 POUT 14 C1- 15 C1+ 16 ...
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Block Diagram CM1 VOLTAGE FEEDBACK - FBB + V REF UVLO COMPARATOR - + 0.75V REF 1.2MHz OSCILLATOR IN1 IN2 EN C DEL ENL V INL NOUT V CONTROL SUP N OUT - FBN + 0.2V UVLO ...
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Typical Application Diagram V IN R18 4.7Ω VIN1 C1 VIN2 2.2µ CM1 10k 4.7nF PGND1 PGND2 EN BIAS AND C SEQUENCE DEL CONTROL C6 0.22µF PGND3 C1+ C7 C1- 220nF C2+ C8 C2- 220nF CTL VINL C9 C10 ...
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Applications Information The ISL97651 provides a complete power solution for TFT LCD applications. The system consists of one boost converter to generate the A voltage for column drivers, VDD one buck converter to provide voltage to logic circuit in the ...
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Some inductors are recommended in Table 3. TABLE 3. BOOST INDUCTOR RECOMMENDATION DIMENSIONS INDUCTOR (mm) VENDOR 6.8µH/ 12.95x9.4x5.21 Coilcraft DO3316P-682ML 4.6A PEAK 10µH/ 10x10x5 Sumida CDR10D48MNNP-100NC 5.5A PEAK 5.2µH/ 10x10.1x3.8 Cooper CD1-5R2 4.55A Bussmann PEAK Rectifier Diode (Boost Converter) A ...
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... V IN LX1, LX2 FBB INTERSIL ISL97651 FIGURE 12. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS Buck Converter The buck converter is the step down converter, which supplies the current to the logic circuit of the LCD system. The ISL97651 integrates an 20V N-Channel MOSFET to save cost and reduce external component count. In the ...
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Output Capacitor (Buck Converter) Four 10µF or two 22µF ceramic capacitors are recommended for this part. The overshoot and undershoot will be reduced with more capacitance, but the recovery time will be longer. TABLE 9. BUCK OUTPUT CAPACITOR RECOMMENDATION CAPACITOR ...
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Control 1.2MHz 0.9V Error VREF FB Negative Charge Pump Design Consideration The negative charge pump consists of an internal switcher M1, M2 which drives external steering diodes D2 and D3 via a pump capacitor (C12) to generate the negative V ...
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A2 FAULT 0.4V A1 1.2MHz STOP CLK PWM EN CONTROL FIGURE 14. NEGATIVE CHARGE PUMP BLOCK DIAGRAM V Slice Circuit ON The V Slice Circuit functions as a three way multiplexer, ON switching the voltage on COM between ground, DRN ...
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A Generation Using DELB VDD_delay DELB pin is an open drain internal N-FET output used to drive an external optional P-FET to provide a delayed A supply which also has no initial pedistal voltage (see Figure 15 and compare the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L36.6x6 36 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 5, 08/08 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 5. 4.15) Exp. Dap 4.15) Exp. Dap. ( ...