ISL6532CCRZ-T Intersil, ISL6532CCRZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL6532CCRZ-T
• Description: IC REG/CTRLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6532CCRZ-T

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 5.25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

Figure 1 shows the soft start sequence for a typical cold
start. Due to the soft start capacitance, C
VREF_IN pin, the S5 to S0 transition profile of the V
will have a more rounded features at the start and end of the
soft start whereas the V
ending points to the ramp up.
By directly monitoring 12VATX and the SLP_S3 and SLP_S5
signals the ISL6532C can achieve PGOOD status
significantly faster than other devices that depend on
Latched_Backfeed_Cut for timing.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6532C will disable the V
LDO controller. The V
and the V
pulled low to disable the backfeed blocking MOSFET.
PGOOD will also transition LOW. When V
internal reference for the V
to the V
floating, the voltage on the V
leakage characteristics of the memory and MCH I/O pins. It
is important to note that the V
The V
standby V
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut
off time will range between 4 and 8µs. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail
through the P5VSBY pin. It is recommended that the 5V
Standby rail be used as the current delivery capability of the
LDO is greater.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the
ISL6532C will enable the V
the V
the NCH pin to a high impedance state turning on the
blocking MOSFET. The AGP LDO goes through a 2048 clock
cycle soft-start. The internal short between the V
reference and the V
short, the capacitor on VREF_IN is then charged up through
the internal resistor divider network. The V
follow this capacitor charge up, and acting as the S3 to S0
transition soft start for the V
is enabled only after 2048 clock cycles, or typically 8.2ms,
have passed following the S3 transition to a HIGH state.
Figure 2 illustrates a typical state transition from S3 to S0. It
should be noted that the soft start profile of the V
output will vary according to the value of the capacitor on the
VREF_IN pin.
DDQ
DDQ
TT
DDQ
DDQ
standby regulator, enable the V
rail. This allows the V
rail will be supported in the S3 state through the
switching regulator will be disabled. NCH is
LDO. When S3 transitions LOW, the Standby
TT
DDQ
rail is released. Upon release of the
DDQ
TT
standby regulator will be enabled
DDQ
TT
TT
TT
TT
profile has distinct starting and
regulator is internally shorted
9
linear regulator and the AGP
rail. The PGOOD comparator
rail may not bleed down to 0V.
rail will depend on the
TT
switching regulator, disable
rail to float. When
SS
TT
TT
TT
, on the
is disabled, the
LDO and force
output will
TT
TT
TT
LDO
rail
ISL6532C
Active to Shutdown (S0 to S5 Transition)
When the system transitions from active, S0, state to
shutdown, S4/S5, state, the ISL6532C IC disables all
regulators and forces the PGOOD pin and the NCH pin LOW.
V
The over-current function protects the switching converter
from a shorted output by using the upper MOSFET on-
resistance, r
enhances the converter’s efficiency and reduces cost by
eliminating a current sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
programs the over-current trip level (see Typical Application
diagrams on pages 3 and 4). An internal 20µA (typical)
current sink develops a voltage across R
referenced to the converter input voltage. When the voltage
across the upper MOSFET (also referenced to the converter
input voltage) exceeds the voltage across R
current function initiates a soft-start sequence. The initiation
of soft start will affect all regulators. The V
directly affected as it receives it’s reference from V
AGP LDO will also be soft started, and as such, the AGP
LDO voltage will be disabled while the V
disabled.
Figure 3 illustrates the protection feature responding to an
over current event. At time T0, an over current condition is
sensed across the upper MOSFET. As a result, the regulator
is quickly shutdown and the internal soft-start function
begins producing soft-start ramps. The delay interval seen
by the output is equivalent to three soft-start cycles. The
fourth internal soft-start cycle initiates a normal soft-start
ramp of the output, at time T1. The output is brought back
into regulation by time T2, as long as the over current event
has cleared.
S3
S5
DDQ
V
TT_FLOAT
FIGURE 2. TYPICAL S3 TO S0 STATE TRANSITION
Over Current Protection (S0 State)
DS(ON)
12V POR
, to monitor the current. This method
2048 CLOCK
CYCLES
12VATX 2V/DIV
PGOOD COMPARATOR
500mV/DIV
V
AGP
ENABLED
DDQ
OCSET
TT
OCSET
regulator is
regulator is
500mV/DIV
500mV/DIV
that is
PGOOD
5V/DIV
V
DDQ
V
DDQ
, the over-
TT
OCSET
. The
)