ISL6532CCRZ-T Intersil, ISL6532CCRZ-T Datasheet - Page 7

• Manufacturer Part Number: ISL6532CCRZ-T
• Description: IC REG/CTRLR ACPI DUAL DDR 28QFN
• Manufacturer: Intersil

Specifications of ISL6532CCRZ-T

• Applications: Memory, DDR/DDR2 Regulator
• Current - Supply: 5.25mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

Functional Pin Description
5VSBY (Pin 2)
5VSBY is the bias supply of the ISL6532C. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6532C enters a reduced
power mode and draws less than 1mA (I
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1µF capacitor.
P12V (Pin 25)
P12V provides the gate drive to the switching MOSFETs of
the PWM power stage. The V
Linear Driver are also powered by P12V. P12V is not
required except during S0/S1/S2 operation. P12V is typically
connected to the +12V rail of an ATX power supply.
5VSBY (Pin 11)
This pin provides the V
state. The regulator is capable of providing standby V
power from either the 5VSBY or 3.3VSBY rail. It is
recommended that the 5VSBY rail be used as the output
current handling capability of the standby LDO is higher than
with the 3.3VSBY rail.
GND, GNDA, GNDP, GNDQ (Pins 1, 3, 4, 17, 29)
The GND terminals of the ISL6532C provide the return path
for the V
drivers. High ground currents are conducted directly through
the exposed paddle of the QFN package which must be
electrically connected to the ground plane through a path as
low in inductance as possible. GNDA is the Analog ground
pin, GNDQ is the return for the VTT regulator and GNDP is
the return for the upper and lower gate drives.
UGATE (Pin 26)
UGATE drives the upper (control) FET of the V
synchronous buck switching regulator. UGATE is driven
between GND and P12V.
LGATE (Pin 27)
LGATE drives the lower (synchronous) FET of the V
synchronous buck switching regulator. LGATE is driven
between GND and P12V.
FB (Pin 15) and COMP (Pin 16)
The V
control loop. FB is the negative input to the voltage loop error
amplifier. The positive input of the error amplifier is
connected to a precision 0.8V reference and the output of
the error amplifier is connected to the COMP pin. The V
output voltage is set by an external resistor divider
connected to FB. With a properly selected divider, V
be set to any voltage between the power rail (reduced by
converter losses) and the 0.8V reference. Loop
compensation is achieved by connecting an AC network
across COMP and FB.
DDQ
TT
switching regulator employs a single voltage
LDO, standby LDO and switching MOSFET gate
DDQ
output power during S3 sleep
TT
7
regulation circuit and the
CC_S5
DDQ
) from the
DDQ
DDQ
DDQ
DDQ
can
ISL6532C
The FB pin is also monitored for under and over-voltage
events.
PHASE (Pin 20)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for over-current protection.
OCSET (Pin 12)
Connect a resistor (R
upper MOSFET. R
(I
set the converter over-current (OC) trip point according to
the following equation:
An over-current trip cycles the soft-start function.
VDDQ (Pins 7, 8, 9)
The VDDQ pins should be connected externally together to
the regulated V
pins serve as inputs to the V
Reference precision divider. During S3 state, the VDDQ pins
serve as an output from the integrated standby LDO.
VTT (Pins 5, 6)
The VTT pins should be connect externally together. During
S0/S1 states, the VTT pins serve as the outputs of the V
linear regulator. During S3 state, the V
disabled.
VTTSNS (Pin 10)
VTTSNS is used as the feedback for control of the V
regulator. Connect this pin to the V
point of desired regulation.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of V
reference voltage for the V
recommended that a minimum capacitance of 0.1µF is
connected between V
between VREF_OUT and ground for proper operation.
VREF_IN (Pin 14)
A capacitor, C
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (R
time constant for the start up ramp when transitioning from
S3 to S0/S1/S2.
The minimum value for C
following equation:
The calculated capacitance, C
capacitor bank on the V
reaching the current limit of the V
I
C
PEAK
OCSET
SS
>
C
------------------------------------------------
=
10 2A R
), and the upper MOSFET on-resistance (r
VTTOUT
I
------------------------------------------------ -
OCSET
⋅
r
SS
⋅
DS ON
DDQ
⋅
, connected between VREF_IN and ground
U
xR
(
V
OCSET
||
DDQ
OCSET
R
output. During S0/S1 states, the VDDQ
OCSET
)
L
DDQ
TT
, an internal 20µA current source
SS
TT
rail in a controlled manner without
and VREF_OUT and also
) from this pin to the drain of the
TT
can be found through the
linear regulator. It is
SS
regulator and to the V
, will charge the output
TT
TT
LDO.
TT
output at the physical
TT
and also acts as the
regulator is
U
||R
L
), sets the
DS(ON)
TT
TT
linear
TT
)