MCZ33800EK Freescale Semiconductor, MCZ33800EK Datasheet - Page 16

• Manufacturer Part Number: MCZ33800EK
• Description: IC ENGINE CTRL SW/DVR 54-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33800EK

• Applications: Automotive
• Current - Supply: 10mA
• Voltage - Supply: 5 V ~ 36 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 54-SOIC (7.5mm Width) Exposed Pad, 54-eSOIC, 54-HSOIC
• Product: Fan / Motor Controllers / Drivers
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ANALOG VOLTAGE SUPPLY (VPWR)
The VPWR pin is battery input to the 33800 IC. The VPWR
pin requires external reverse battery and transient protection.
Maximum input voltage on VPWR is 45V. All IC analog
current and internal logic current is provided from the VPWR
pin. With V
V
DIGITAL VOLTAGE SUPPLY (VDD)
logic levels between the microprocessor and the 33800
device. Current from V
up current for CS. V
operation. Removing V
Sleep Mode. Power-ON Reset will be performed with the
application of V
GROUND (GND)
IC. The VPWR and VDD supplies are both referenced to the
GND pin. GND pin should be used for decoupling both
supplies.
CONSTANT CURRENT DRIVER GROUND
(CCDX_GND)
provide dedicated grounds for the Constant Current output
drivers. Both CCDX_GND1 and CCDX_GND2 grounds are
isolated from the other grounds of the IC.
GROUND (PGND1 - 3, CCD1_GND, CCD2_GND)
drivers. OUT1 driver and OUT2 driver have dedicated
PGND1 & PGND2 pins. Drivers OUT3 through Driver OUT8
share one PGND3 pin. In general all ground pins must be
connected together and terminated to ground on the circuit
board.
SOURCE VOLTAGE SENSE (VSSNS123
VSSNS456)
provide dedicated grounds for the hex MOSFET pre-drivers.
The pins are used by the IC to monitor the drain to source
voltage of the external MOSFET. This pin must be connected
to the source of the external MOSFET and system ground.
VSSNS123 and VSSNS456 ground pins are isolated from
other internal IC grounds.
16
33800
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
PWR
The VDD input pin is used to determine communication
The GND pin provides a low current analog ground for the
The Constant Current Driver Ground (CCDX_GND) pins
There are three PGND pins associated with the OSS
The Source Sense Ground pins (VSSNS123, VSSNS456)
will perform a Power-ON Reset (POR).
DD
and EN applied to the IC, the application of
DD
supply
DD
DD
DD
must be applied for Normal Mode
.
is used to drive SO output and pull-
from the IC will place the device in
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
,
SERIAL CLOCK INPUT (SCLK)
register of the 33800. The SI data is latched into the input
shift register on the rising edge of SCLK signal. The SO pin
shifts status bits out on the falling edge of SCLK. The SO data
is available for the MCU to read on the rising edge of SCLK.
With CS in a logic high state, signals on the SCLK and SI pins
will be ignored and the SO pin is tri-state.
CHIP SELECT (CS)
communication using the chip select (CS) pin. With the CS in
a logic low state, command words may be sent to the 33800
via the serial input (SI) pin, and status information is received
by the MCU via the serial output (SO) pin. The falling edge of
CS enables the SO output and transfers status information
into the SO buffer.
and low-to-high transitions of the CS signal occur only when
SCLK is in a logic low state. Internal to the 33800 device is an
active pull-up to VDD on CS. In cases were voltage exists on
CS without the application of V
CS to the VDD pin.
SERIAL INPUT DATA (SI)
information is latched into the input register on the rising edge
of SCLK. A logic high state present on SI will program a one
in the command word on the rising edge of the CS signal. To
program a complete word, 16-bits of information must be
entered into the device.
SERIAL OUTPUT DATA (SO)
remains tri-stated until the CS pin transitions to a logic low
state. All normal operating drivers are reported as zero, all
faulted drivers are reported as one. The negative transition of
CS enables the SO driver.
protocol, with both input and output words transferring the
most significant bit (MSB) first.
ENABLE (EN)
enable the device. With the EN pin low the device is in Sleep
Mode. With the EN pin high, the device is in Normal Mode
(V
1. Disables the SO driver (high-impedance)
2. Activates the received command word, allowing the
DD
The system clock (SCLK) pin clocks the internal shift
The system MCU selects the 33800 to receive
Rising edge of the CS initiates the following operation:
To avoid any spurious data, it is essential the high-to-low
The SI pin is used for serial instruction data input. SI
The SO pin is the output from the shift register. The SO pin
The SI / SO shifting of the data follows a first-in-first-out
The ENABLE pin is an active high digital input pin used to
33800 to activate/deactivate output drivers.
and V
PWR
applied). Exit from Sleep Mode initiates a
Analog Integrated Circuit Device Data
DD
, no current will flow from
Freescale Semiconductor